module test
	(
		input	wire			clk,
		output	wire	[11:0]	data
	);

	reg 	[11:0]	int_data;
	reg 	[15:0]	counter;
//	reg 	[5:0]	counter;
	reg		[5:0]	state;

	always @(posedge clk)
	begin
		case (state)
/*
			0: 
			begin
				int_data <= 12'd0;
				state <= 6'd1;
			end
			
			1:
			begin
				int_data <= 12'd1024;
				state <= 6'd2;
			end

			2:
			begin
				int_data <= 12'd2048;
				state <= 6'd3;
			end

			3:
			begin
				int_data <= 12'd3072;
				state <= 6'd4;
			end

			4:
			begin
				int_data <= 12'd4095;
				state <= 6'd5;
			end

			5:
			begin
				int_data <= 12'd3072;
				state <= 6'd6;
			end

			6:
			begin
				int_data <= 12'd2048;
				state <= 6'd7;
			end

			7:
			begin
				int_data <= 12'd1024;
				state <= 6'd8;
			end

  			8:
			begin
				int_data <= 12'd0;
				counter <= counter + 6'd1;
				if (&counter)
				begin
					state <= 6'd0;
				end
			end
*/

  			6'd0:
			begin
				int_data <= 12'h030;
				state <= 6'd1;
			end

  			6'd1:
			begin
				int_data <= 12'h034;
				state <= 6'd2;
			end

  			6'd2:
			begin
				int_data <= 12'h081;
				state <= 6'd3;
			end

  			6'd3:
			begin
				int_data <= 12'h0f5;
				state <= 6'd4;
			end

  			6'd4:
			begin
				int_data <= 12'h10a;
				state <= 6'd5;
			end

  			6'd5:
			begin
				int_data <= 12'h11a;
				state <= 6'd6;
			end

  			6'd6:
			begin
				int_data <= 12'h124;
				state <= 6'd7;
			end

  			6'd7:
			begin
				int_data <= 12'h124;
				state <= 6'd8;
			end

  			6'd8:
			begin
				int_data <= 12'h12b;
				state <= 6'd9;
			end

  			6'd9:
			begin
				int_data <= 12'h12a;
				state <= 6'd10;
			end

  			6'd10:
			begin
				int_data <= 12'h12a;
				state <= 6'd11;
			end

  			6'd11:
			begin
				int_data <= 12'h12b;
				state <= 6'd12;
			end

  			6'd12:
			begin
				int_data <= 12'h12a;
				state <= 6'd13;
			end

  			6'd13:
			begin
				int_data <= 12'h12e;
				state <= 6'd14;
			end

  			6'd14:
			begin
				int_data <= 12'h12b;
				state <= 6'd15;
			end

  			6'd15:
			begin
				int_data <= 12'h12b;
				state <= 6'd16;
			end

  			6'd16:
			begin
				int_data <= 12'h12e;
				state <= 6'd17;
			end

  			6'd17:
			begin
				int_data <= 12'h12b;
				state <= 6'd18;
			end

  			6'd18:
			begin
				int_data <= 12'h12a;
				state <= 6'd19;
			end

  			6'd19:
			begin
				int_data <= 12'h12e;
				state <= 6'd20;
			end

  			6'd20:
			begin
				int_data <= 12'h12b;
				state <= 6'd21;
			end

  			6'd21:
			begin
				int_data <= 12'h12e;
				state <= 6'd22;
			end

  			6'd22:
			begin
				int_data <= 12'h12f;
				state <= 6'd23;
			end

  			6'd23:
			begin
				int_data <= 12'h12f;
				state <= 6'd24;
			end

  			6'd24:
			begin
				int_data <= 12'h12b;
				state <= 6'd25;
			end

  			6'd25:
			begin
				int_data <= 12'h12b;
				state <= 6'd26;
			end

  			6'd26:
			begin
				int_data <= 12'h12b;
				state <= 6'd27;
			end

  			6'd27:
			begin
				int_data <= 12'h12e;
				state <= 6'd28;
			end

  			6'd28:
			begin
				int_data <= 12'h12e;
				state <= 6'd29;
			end

  			6'd29:
			begin
				int_data <= 12'h12e;
				state <= 6'd30;
			end

  			6'd30:
			begin
				int_data <= 12'h12e;
				state <= 6'd31;
			end

  			6'd31:
			begin
				int_data <= 12'h12b;
				state <= 6'd32;
			end

  			6'd32:
			begin
				int_data <= 12'h12b;
				state <= 6'd33;
			end

  			6'd33:
			begin
				int_data <= 12'h12b;
				state <= 6'd34;
			end

  			6'd34:
			begin
				int_data <= 12'h12e;
				state <= 6'd35;
			end

  			6'd35:
			begin
				int_data <= 12'h12e;
				state <= 6'd36;
			end

  			6'd36:
			begin
				int_data <= 12'h12e;
				state <= 6'd37;
			end

  			6'd37:
			begin
				int_data <= 12'h12e;
				state <= 6'd38;
			end

  			6'd38:
			begin
				int_data <= 12'h12f;
				state <= 6'd39;
			end

  			6'd39:
			begin
				int_data <= 12'h12b;
				state <= 6'd40;
			end

  			6'd40:
			begin
				int_data <= 12'h12e;
				state <= 6'd41;
			end

  			6'd41:
			begin
				int_data <= 12'h12f;
				state <= 6'd42;
			end

  			6'd42:
			begin
				int_data <= 12'h0fb;
				state <= 6'd43;
			end

  			6'd43:
			begin
				int_data <= 12'h07e;
				state <= 6'd44;
			end

  			6'd44:
			begin
				int_data <= 12'h070;
				state <= 6'd45;
			end

  			6'd45:
			begin
				int_data <= 12'h05a;
				state <= 6'd46;
			end

  			6'd46:
			begin
				int_data <= 12'h045;
				state <= 6'd47;
			end

  			6'd47:
			begin
				int_data <= 12'h03f;
				state <= 6'd48;
			end

  			6'd48:
			begin
				int_data <= 12'h03b;
				state <= 6'd49;
			end

  			6'd49:
			begin
				int_data <= 12'h034;
				state <= 6'd50;
			end

  			6'd50:
			begin
				int_data <= 12'h035;
				state <= 6'd51;
			end

  			6'd51:
			begin
				int_data <= 12'h034;
				state <= 6'd52;
			end

  			6'd52:
			begin
				int_data <= 12'h034;
				state <= 6'd53;
			end

  			6'd53:
			begin
				int_data <= 12'h030;
				state <= 6'd54;
			end

  			6'd54:
			begin
				int_data <= 12'h030;
				counter <= counter + 16'd1;
				if (&counter)
				begin
					state <= 6'd0;
				end
			end

			default:
			begin
				state <= 6'd0;
			end
		endcase
	end

	assign	data = int_data;

endmodule