source: trunk/Octopus/histogram.v@ 200

Last change on this file since 200 was 102, checked in by demin, 15 years ago

initial commit

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1module histogram
2 (
3 input wire clock, frame, reset,
4
5 input wire hst_good,
6 input wire [8:0] hst_data,
7
8 input wire bus_ssel, bus_wren,
9 input wire [9:0] bus_addr,
10 input wire [15:0] bus_mosi,
11
12 output wire [15:0] bus_miso,
13 output wire bus_busy
14 );
15
16 // signal declaration
17 reg [3:0] int_case_reg, int_case_next;
18 reg int_wren_reg, int_wren_next;
19 reg [8:0] int_addr_reg, int_addr_next;
20 reg [31:0] int_data_reg, int_data_next;
21
22 reg [9:0] bus_addr_reg, bus_addr_next;
23 reg [15:0] bus_miso_reg, bus_miso_next;
24
25 reg bus_wren_reg, bus_wren_next;
26 reg [15:0] bus_mosi_reg, bus_mosi_next;
27
28 wire [31:0] q_a_wire;
29 wire [15:0] q_b_wire;
30
31 altsyncram #(
32 .address_reg_b("CLOCK0"),
33 .clock_enable_input_a("BYPASS"),
34 .clock_enable_input_b("BYPASS"),
35 .clock_enable_output_a("BYPASS"),
36 .clock_enable_output_b("BYPASS"),
37 .indata_reg_b("CLOCK0"),
38 .intended_device_family("Cyclone III"),
39 .lpm_type("altsyncram"),
40 .numwords_a(512),
41 .numwords_b(1024),
42 .operation_mode("BIDIR_DUAL_PORT"),
43 .outdata_aclr_a("NONE"),
44 .outdata_aclr_b("NONE"),
45 .outdata_reg_a("CLOCK0"),
46 .outdata_reg_b("CLOCK0"),
47 .power_up_uninitialized("FALSE"),
48 .read_during_write_mode_mixed_ports("OLD_DATA"),
49 .read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"),
50 .read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"),
51 .widthad_a(9),
52 .widthad_b(10),
53 .width_a(32),
54 .width_b(16),
55 .width_byteena_a(1),
56 .width_byteena_b(1),
57 .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit(
58 .wren_a(int_wren_reg),
59 .clock0(clock),
60 .wren_b(bus_wren_reg),
61 .address_a(int_addr_reg),
62 .address_b(bus_addr_reg),
63 .data_a(int_data_reg),
64 .data_b(bus_mosi_reg),
65 .q_a(q_a_wire),
66 .q_b(q_b_wire),
67 .aclr0(1'b0),
68 .aclr1(1'b0),
69 .addressstall_a(1'b0),
70 .addressstall_b(1'b0),
71 .byteena_a(1'b1),
72 .byteena_b(1'b1),
73 .clock1(1'b1),
74 .clocken0(1'b1),
75 .clocken1(1'b1),
76 .clocken2(1'b1),
77 .clocken3(1'b1),
78 .eccstatus(),
79 .rden_a(1'b1),
80 .rden_b(1'b1));
81
82 // body
83 always @(posedge clock)
84 begin
85 if (reset)
86 begin
87 int_wren_reg <= 1'b1;
88 int_addr_reg <= 9'd0;
89 int_data_reg <= 32'd0;
90 int_case_reg <= 4'b0;
91 bus_addr_reg <= 10'd0;
92 bus_miso_reg <= 16'd0;
93 bus_wren_reg <= 1'b0;
94 bus_mosi_reg <= 16'd0;
95 end
96 else
97 begin
98 int_wren_reg <= int_wren_next;
99 int_addr_reg <= int_addr_next;
100 int_data_reg <= int_data_next;
101 int_case_reg <= int_case_next;
102 bus_addr_reg <= bus_addr_next;
103 bus_miso_reg <= bus_miso_next;
104 bus_wren_reg <= bus_wren_next;
105 bus_mosi_reg <= bus_mosi_next;
106 end
107 end
108
109 always @*
110 begin
111 bus_addr_next = bus_addr_reg;
112 bus_miso_next = bus_miso_reg;
113
114 bus_wren_next = 1'b0;
115 bus_mosi_next = bus_mosi_reg;
116
117 if (bus_ssel)
118 begin
119 bus_miso_next = q_b_wire;
120 bus_addr_next = bus_addr;
121 bus_wren_next = bus_wren;
122 if (bus_wren)
123 begin
124 bus_mosi_next = bus_mosi;
125 end
126 end
127 end
128
129 always @*
130 begin
131 int_wren_next = int_wren_reg;
132 int_addr_next = int_addr_reg;
133 int_data_next = int_data_reg;
134 int_case_next = int_case_reg;
135
136 case (int_case_reg)
137
138 0:
139 begin
140 // write zeros
141 int_addr_next = int_addr_reg + 9'd1;
142 if (&int_addr_reg)
143 begin
144 int_wren_next = 1'b0;
145 int_case_next = 4'd1;
146 end
147 end
148
149 1:
150 begin
151 int_wren_next = 1'b0;
152/*
153 if (&int_data_reg)
154 begin
155 int_case_next = 4'd0;
156 end
157 else if (frame & hst_good)
158*/
159 if (frame & hst_good)
160 begin
161 int_addr_next = hst_data;
162 int_case_next = 4'd2;
163 end
164 end
165
166 2:
167 begin
168 int_case_next = 4'd3;
169 end
170
171 3:
172 begin
173 int_case_next = 4'd4;
174 end
175
176 4:
177 begin
178 int_case_next = 4'd1;
179 if (~&q_a_wire)
180 begin
181 int_wren_next = 1'b1;
182 int_data_next = q_a_wire + 32'd1;
183 end
184 end
185
186 default:
187 begin
188 int_wren_next = 1'b0;
189 int_addr_next = 9'd0;
190 int_data_next = 32'd0;
191 int_case_next = 4'd0;
192 end
193 endcase
194 end
195
196 // output logic
197 assign bus_miso = bus_miso_reg;
198 assign bus_busy = 1'b0;
199endmodule
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