source: trunk/Octopus/adc_lvds.v@ 162

Last change on this file since 162 was 102, checked in by demin, 15 years ago

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1module adc_lvds
2 #(
3 parameter size = 8, // number of channels
4 parameter width = 24 // channel resolution
5 )
6 (
7 input wire clock,
8
9 input wire lvds_dco,
10 input wire lvds_fco,
11 input wire [size-1:0] lvds_d,
12
13 output wire adc_frame,
14 output wire [size*width-1:0] adc_data
15
16 );
17
18 reg state, int_rdreq, adc_frame_reg;
19 wire int_wrfull, int_rdempty;
20
21 reg [size-1:0] int_data_h, int_data_l;
22
23 reg [size*width-1:0] int_data_reg;
24 wire [size*width-1:0] int_data_wire;
25
26 wire [size*width-1:0] int_q_wire;
27 reg [size*width-1:0] adc_data_reg;
28
29
30 genvar j;
31
32 generate
33 for (j = 0; j < size; j = j + 1)
34 begin : INT_DATA
35 assign int_data_wire[j*width+width-1:j*width] = {int_data_reg[j*width+width-3:j*width], int_data_h[j], int_data_l[j]};
36 end
37 endgenerate
38
39 dcfifo #(
40 .intended_device_family("Cyclone III"),
41 .lpm_numwords(16),
42 .lpm_showahead("ON"),
43 .lpm_type("dcfifo"),
44 .lpm_width(size*width),
45 .lpm_widthu(4),
46 .rdsync_delaypipe(4),
47 .wrsync_delaypipe(4),
48 .overflow_checking("ON"),
49 .underflow_checking("ON"),
50 .use_eab("ON")) fifo_unit (
51 .data(int_data_wire),
52 .rdclk(clock),
53 .rdreq((~int_rdempty) & int_rdreq),
54 .wrclk(lvds_fco),
55 .wrreq(~int_wrfull),
56 .q(int_q_wire),
57 .rdempty(int_rdempty),
58 .wrfull(int_wrfull),
59 .aclr(),
60 .rdfull(),
61 .rdusedw(),
62 .wrempty(),
63 .wrusedw());
64
65 always @ (posedge clock)
66 begin
67 case (state)
68 1'b0:
69 begin
70 int_rdreq <= 1'b1;
71 adc_frame_reg <= 1'b0;
72 state <= 1'b1;
73 end
74
75 1'b1:
76 begin
77 if (~int_rdempty)
78 begin
79 int_rdreq <= 1'b0;
80 adc_data_reg <= int_q_wire;
81 adc_frame_reg <= 1'b1;
82 state <= 1'b0;
83 end
84 end
85 endcase
86 end
87
88 always @ (negedge lvds_dco)
89 begin
90 int_data_l <= lvds_d;
91 end
92
93 always @ (posedge lvds_dco)
94 begin
95 int_data_h <= lvds_d;
96 int_data_reg <= int_data_wire;
97 end
98
99 assign adc_frame = adc_frame_reg;
100 assign adc_data = adc_data_reg;
101
102endmodule
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