source: trunk/Octopus/Octopus.v@ 145

Last change on this file since 145 was 102, checked in by demin, 15 years ago

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1module Octopus
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 input wire [16:0] CON_A,
7
8 input wire [1:0] CON_BCLK,
9 input wire [10:0] CON_B,
10 inout wire I2C_SDA,
11 inout wire I2C_SCL,
12
13// input wire ADC_DCO,
14 input wire ADC_FCO,
15 input wire [7:0] ADC_D,
16
17 output wire USB_SLRD,
18 output wire USB_SLWR,
19 input wire USB_IFCLK,
20 input wire USB_FLAGA, // EMPTY flag for EP6
21 input wire USB_FLAGB, // FULL flag for EP8
22 output wire USB_PA2,
23 output wire USB_PA4,
24 output wire USB_PA5,
25 output wire USB_PA6,
26 inout wire [7:0] USB_PB,
27
28 output wire RAM_CLK,
29 output wire RAM_CE1,
30 output wire RAM_WE,
31 output wire [19:0] RAM_ADDR,
32 inout wire RAM_DQAP,
33 inout wire [7:0] RAM_DQA,
34 inout wire RAM_DQBP,
35 inout wire [7:0] RAM_DQB
36 );
37
38 localparam N = 16;
39 localparam M = 4;
40
41 assign RAM_CLK = sys_clock;
42 assign RAM_CE1 = 1'b0;
43
44 assign USB_PA2 = ~usb_rden;
45 assign USB_PA4 = usb_addr[0];
46 assign USB_PA5 = usb_addr[1];
47 assign USB_PA6 = ~usb_pktend;
48
49 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
50 wire usb_tx_wrreq, usb_rx_rdreq;
51 wire usb_tx_full, usb_rx_empty;
52 wire [7:0] usb_tx_data, usb_rx_data;
53 wire [1:0] usb_addr;
54
55 assign USB_SLRD = ~usb_rdreq;
56 assign USB_SLWR = ~usb_wrreq;
57
58 usb_fifo usb_unit
59 (
60 .usb_clock(USB_IFCLK),
61 .usb_data(USB_PB),
62 .usb_full(~USB_FLAGB),
63 .usb_empty(~USB_FLAGA),
64 .usb_wrreq(usb_wrreq),
65 .usb_rdreq(usb_rdreq),
66 .usb_rden(usb_rden),
67 .usb_pktend(usb_pktend),
68 .usb_addr(usb_addr),
69
70 .clock(sys_clock),
71
72 .tx_full(usb_tx_full),
73 .tx_wrreq(usb_tx_wrreq),
74 .tx_data(usb_tx_data),
75
76 .rx_empty(usb_rx_empty),
77 .rx_rdreq(usb_rx_rdreq),
78 .rx_q(usb_rx_data)
79 );
80
81 wire [N*M*12-1:0] int_mux_data;
82
83 wire [11:0] osc_mux_data [M-1:0];
84 wire [11:0] trg_mux_data;
85 wire trg_flag;
86
87 wire ana_good [N-1:0];
88 wire [11:0] ana_data [N-1:0];
89
90 wire sys_clock, sys_frame;
91
92 wire adc_fast_clock, adc_slow_clock;
93
94 wire [N*12-1:0] int_data;
95
96 wire [11:0] sys_data [N-1:0];
97 wire [11:0] nowhere;
98
99 wire [23:0] uwt_d1 [N-1:0];
100 wire [23:0] uwt_a1 [N-1:0];
101 wire [23:0] uwt_peak1 [N-1:0];
102 wire [23:0] uwt_d2 [N-1:0];
103 wire [23:0] uwt_a2 [N-1:0];
104 wire [23:0] uwt_peak2 [N-1:0];
105 wire [23:0] uwt_d3 [N-1:0];
106 wire [23:0] uwt_a3 [N-1:0];
107 wire [23:0] uwt_peak3 [N-1:0];
108
109 wire [1:0] uwt_flag1 [N-1:0];
110 wire [1:0] uwt_flag2 [N-1:0];
111 wire [1:0] uwt_flag3 [N-1:0];
112
113 wire i2c_reset;
114
115
116 sys_pll sys_pll_unit (
117 .inclk0(CLK_50MHz),
118 .c0(sys_clock));
119
120 test test_unit (
121 .clk(ADC_FCO),
122 .data(nowhere));
123
124 adc_pll adc_pll_unit (
125 .inclk0(ADC_FCO),
126 .c0(adc_fast_clock),
127 .c1(adc_slow_clock));
128
129 adc_lvds #(
130 .size(N/2),
131 .width(24)) adc_lvds_unit (
132 .clock(sys_clock),
133 .lvds_dco(adc_fast_clock),
134 .lvds_fco(adc_slow_clock),
135 .lvds_d(ADC_D),
136 .adc_frame(sys_frame),
137 .adc_data(int_data));
138
139 wire [15:0] cfg_bits [31:0];
140 wire [511:0] int_cfg_bits;
141
142 wire [31:0] cfg_mux_selector;
143
144 wire cfg_reset;
145
146 wire [19-1:0] bus_ssel;
147 wire bus_wren;
148 wire [31:0] bus_addr;
149 wire [15:0] bus_mosi;
150 wire [15:0] bus_miso [19-2:0];
151 wire [19-1:0] bus_busy;
152
153 wire [15:0] mrg_bus_miso;
154 wire mrg_bus_busy;
155
156 wire [(19-1)*16-1:0] int_bus_miso;
157
158 genvar j;
159
160 generate
161 for (j = 0; j < 32; j = j + 1)
162 begin : CONFIGURATION_OUTPUT
163 assign cfg_bits[j] = int_cfg_bits[j*16+15:j*16];
164 end
165 endgenerate
166
167 configuration configuration_unit (
168 .clock(sys_clock),
169 .reset(cfg_reset),
170 .bus_ssel(bus_ssel[0]),
171 .bus_wren(bus_wren),
172 .bus_addr(bus_addr[4:0]),
173 .bus_mosi(bus_mosi),
174 .bus_miso(bus_miso[0]),
175 .bus_busy(bus_busy[0]),
176 .cfg_bits(int_cfg_bits));
177
178 generate
179 for (j = 0; j < N; j = j + 1)
180 begin : MUX_DATA
181 assign int_mux_data[j*4*12+4*12-1:j*4*12] = {
182 {ana_good[j], 11'd0},
183 ana_data[j],
184 uwt_a2[j][17:6],
185 sys_data[j]};
186 end
187 endgenerate
188
189 assign cfg_mux_selector = {cfg_bits[5], cfg_bits[4]};
190
191 lpm_mux #(
192 .lpm_size(N*4),
193 .lpm_type("LPM_MUX"),
194 .lpm_width(12),
195 .lpm_widths(6)) trg_mux_unit (
196 .sel(cfg_bits[6][5:0]),
197 .data(int_mux_data),
198 .result(trg_mux_data));
199
200 generate
201 for (j = 0; j < M; j = j + 1)
202 begin : OSC_CHAIN
203
204 lpm_mux #(
205 .lpm_size(N*4),
206 .lpm_type("LPM_MUX"),
207 .lpm_width(12),
208 .lpm_widths(6)) osc_mux_unit (
209 .sel(cfg_mux_selector[j*8+5:j*8]),
210 .data(int_mux_data),
211 .result(osc_mux_data[j]));
212
213 end
214 endgenerate
215
216 trigger trigger_unit (
217 .clock(sys_clock),
218 .frame(sys_frame),
219 .reset(cfg_bits[0][0]),
220 .cfg_data(cfg_bits[7][11:0]),
221 .trg_data(trg_mux_data),
222 .trg_flag(trg_flag));
223
224 oscilloscope oscilloscope_unit (
225 .clock(sys_clock),
226 .frame(sys_frame),
227 .reset(cfg_bits[0][1]),
228 .cfg_data(cfg_bits[7][12]),
229 .trg_flag(trg_flag),
230 .osc_data({16'd0, osc_mux_data[3], osc_mux_data[2], osc_mux_data[1], osc_mux_data[0]}),
231 .ram_wren(RAM_WE),
232 .ram_addr(RAM_ADDR),
233 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
234 .bus_ssel(bus_ssel[1]),
235 .bus_wren(bus_wren),
236 .bus_addr(bus_addr[19:0]),
237 .bus_mosi(bus_mosi),
238 .bus_miso(bus_miso[1]),
239 .bus_busy(bus_busy[1]));
240
241 generate
242 for (j = 0; j < N; j = j + 1)
243 begin : MCA_CHAIN
244
245 assign sys_data[j] = (cfg_bits[3][j]) ? (int_data[j*12+11:j*12] ^ 12'hfff) : (int_data[j*12+11:j*12]);
246
247 uwt_bior31 #(.L(1)) uwt_1_unit (
248 .clock(sys_clock),
249 .frame(sys_frame),
250 .reset(1'b0),
251 .x({20'h00000, sys_data[j]}),
252 .d(uwt_d1[j]),
253 .a(uwt_a1[j]),
254 .peak(uwt_peak1[j]),
255 .flag(uwt_flag1[j]));
256
257 uwt_bior31 #(.L(2)) uwt_2_unit (
258 .clock(sys_clock),
259 .frame(sys_frame),
260 .reset(1'b0),
261 .x(uwt_a1[j]),
262 .d(uwt_d2[j]),
263 .a(uwt_a2[j]),
264 .peak(uwt_peak2[j]),
265 .flag(uwt_flag2[j]));
266
267 uwt_bior31 #(.L(3)) uwt_3_unit (
268 .clock(sys_clock),
269 .frame(sys_frame),
270 .reset(1'b0),
271 .x(uwt_a2[j]),
272 .d(uwt_d3[j]),
273 .a(uwt_a3[j]),
274 .peak(uwt_peak3[j]),
275 .flag(uwt_flag3[j]));
276
277 analyser analyser_unit (
278 .clock(sys_clock),
279 .frame(sys_frame),
280 .reset(cfg_bits[1][j]),
281 .cfg_data(cfg_bits[8+j]),
282 .uwt_flag(uwt_flag3[j]),
283 .uwt_data(uwt_peak3[j][11:0]),
284 .ana_good(ana_good[j]),
285 .ana_data(ana_data[j]));
286
287 histogram histogram_unit (
288 .clock(sys_clock),
289 .frame(sys_frame),
290 .reset(cfg_bits[2][j]),
291 .hst_good(ana_good[j]),
292 .hst_data(ana_data[j][11:3]),
293 .bus_ssel(bus_ssel[2+j]),
294 .bus_wren(bus_wren),
295 .bus_addr(bus_addr[9:0]),
296 .bus_mosi(bus_mosi),
297 .bus_miso(bus_miso[2+j]),
298 .bus_busy(bus_busy[2+j]));
299
300 end
301 endgenerate
302
303 i2c_fifo i2c_unit(
304 .clock(sys_clock),
305 .reset(i2c_reset),
306
307 .i2c_sda(I2C_SDA),
308 .i2c_scl(I2C_SCL),
309
310 .bus_ssel(bus_ssel[18]),
311 .bus_wren(bus_wren),
312 .bus_mosi(bus_mosi),
313 .bus_busy(bus_busy[18]));
314
315 generate
316 for (j = 0; j < 18; j = j + 1)
317 begin : BUS_OUTPUT
318 assign int_bus_miso[j*16+15:j*16] = bus_miso[j];
319 end
320 endgenerate
321
322 lpm_mux #(
323 .lpm_size(18),
324 .lpm_type("LPM_MUX"),
325 .lpm_width(16),
326 .lpm_widths(5)) bus_miso_mux_unit (
327 .sel(bus_addr[28:24]),
328 .data(int_bus_miso),
329 .result(mrg_bus_miso));
330
331 lpm_mux #(
332 .lpm_size(19),
333 .lpm_type("LPM_MUX"),
334 .lpm_width(1),
335 .lpm_widths(5)) bus_busy_mux_unit (
336 .sel(bus_addr[28:24]),
337 .data(bus_busy),
338 .result(mrg_bus_busy));
339
340 lpm_decode #(
341 .lpm_decodes(19),
342 .lpm_type("LPM_DECODE"),
343 .lpm_width(5)) lpm_decode_unit (
344 .data(bus_addr[28:24]),
345 .eq(bus_ssel),
346 .aclr(),
347 .clken(),
348 .clock(),
349 .enable());
350
351 control control_unit (
352 .clock(sys_clock),
353 .rx_empty(usb_rx_empty),
354 .tx_full(usb_tx_full),
355 .rx_data(usb_rx_data),
356 .rx_rdreq(usb_rx_rdreq),
357 .tx_wrreq(usb_tx_wrreq),
358 .tx_data(usb_tx_data),
359 .bus_wren(bus_wren),
360 .bus_addr(bus_addr),
361 .bus_mosi(bus_mosi),
362 .bus_miso(mrg_bus_miso),
363 .bus_busy(mrg_bus_busy),
364 .led(LED));
365
366/*
367 altserial_flash_loader #(
368 .enable_shared_access("OFF"),
369 .enhanced_mode(1),
370 .intended_device_family("Cyclone III")) sfl_unit (
371 .noe(1'b0),
372 .asmi_access_granted(),
373 .asmi_access_request(),
374 .data0out(),
375 .dclkin(),
376 .scein(),
377 .sdoin());
378*/
379
380endmodule
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