source:
trunk/MultiChannelUSB@
62
| Name | Size | Rev | Age | Author | Last Change |
|---|---|---|---|---|---|
| ../ | |||||
| uwt_bior31.v | 1.8 KB | 27 | 16 years | initial commit | |
| usb_fifo.v | 2.8 KB | 58 | 16 years | code cleanup | |
| test_pll.v | 5.1 KB | 59 | 16 years | move control and test code to separate modules | |
| test.v | 793 bytes | 59 | 16 years | move control and test code to separate modules | |
| pll.v | 5.1 KB | 27 | 16 years | initial commit | |
| Paella.v | 6.6 KB | 59 | 16 years | move control and test code to separate modules | |
| Paella.qsf | 17.8 KB | 61 | 16 years | add interface for parallel ADC with unreliable clock | |
| Paella.qpf | 1.2 KB | 27 | 16 years | initial commit | |
| Paella.dpf | 1.4 KB | 41 | 16 years | add one real ADC channel | |
| Paella.cof | 436 bytes | 39 | 16 years | add configuration for EPCS16 | |
| oscilloscope.v | 3.9 KB | 52 | 16 years | switch to normal memory clock | |
| histogram.v | 3.2 KB | 52 | 16 years | switch to normal memory clock | |
| control.v | 3.5 KB | 59 | 16 years | move control and test code to separate modules | |
| analyser.v | 2.3 KB | 50 | 16 years | fix peak detection logic and add peak threshold | |
| adc_pll.v | 5.1 KB | 55 | 16 years | add pll for lvds interface | |
| adc_para.v | 595 bytes | 60 | 16 years | interface for parallel ADC with unreliable clock | |
| adc_lvds.v | 1.2 KB | 58 | 16 years | code cleanup | |
| adc_fifo.v | 2.9 KB | 62 | 16 years | add polarity flag | |
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