1 | module uwt_bior31
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2 | #(
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3 | parameter L = 1 // transform level
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4 | )
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5 | (
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6 | input wire clock, frame, reset,
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7 | input wire [31:0] x,
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8 | output wire [31:0] d,
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9 | output wire [31:0] a,
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10 | output wire [31:0] peak,
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11 | output wire [1:0] flag
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12 | );
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13 |
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14 | localparam index1 = 1 << (L - 1);
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15 | localparam index2 = 2 << (L - 1);
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16 | localparam index3 = 3 << (L - 1);
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17 | localparam peak_index = ((index3 + 1) >> 1) + 1;
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18 | localparam peak_shift = ((L - 1) << 1) + (L - 1);
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19 | localparam zero = 32'h80000000;
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20 |
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21 | // Tapped delay line
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22 | reg [31:0] tap [index3:0];
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23 |
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24 | reg [31:0] d_reg, d_next;
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25 | reg [31:0] a_reg, a_next;
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26 | reg [31:0] peak_reg, peak_next;
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27 |
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28 | reg [31:0] tmp1_reg, tmp1_next;
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29 | reg [31:0] tmp2_reg, tmp2_next;
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30 |
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31 | reg less_reg, less_next;
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32 | reg more_reg, more_next;
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33 |
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34 | reg [1:0] flag_reg;
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35 |
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36 | integer i;
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37 |
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38 | always @(posedge clock)
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39 | begin
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40 | if (reset)
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41 | begin
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42 | d_reg <= 0;
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43 | a_reg <= 0;
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44 | peak_reg <= 0;
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45 | flag_reg <= 0;
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46 | tmp1_reg <= 0;
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47 | tmp2_reg <= 0;
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48 | less_reg <= 1'b0;
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49 | more_reg <= 1'b0;
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50 |
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51 | for(i = 0; i <= index3; i = i + 1)
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52 | begin
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53 | tap[i] <= 0;
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54 | end
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55 | end
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56 | else if (frame)
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57 | begin
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58 | d_reg <= d_next;
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59 | a_reg <= a_next;
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60 | peak_reg <= peak_next;
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61 |
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62 | tmp1_reg <= tmp1_next;
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63 | tmp2_reg <= tmp2_next;
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64 | less_reg <= less_next;
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65 | more_reg <= more_next;
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66 |
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67 | flag_reg[0] <= (more_reg) & (~more_next);
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68 | flag_reg[1] <= (less_reg) & (~less_next);
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69 |
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70 | // Tapped delay line: shift one
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71 | for(i = 0; i < index3; i = i + 1)
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72 | begin
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73 | tap[i+1] <= tap[i];
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74 | end
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75 |
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76 | // Input in register 0
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77 | tap[0] <= x;
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78 | end
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79 | end
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80 |
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81 | always @*
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82 | begin
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83 | // Compute d and a with the filter coefficients.
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84 | // The coefficients are [1, 3, -3, -1] and [1, 3, 3, 1]
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85 |
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86 | tmp1_next = tap[index3] + {tap[index2][30:0], 1'b0} + tap[index2];
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87 | tmp2_next = {tap[index1][30:0], 1'b0} + tap[index1] + tap[0];
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88 |
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89 | d_next = zero - tmp1_reg + tmp2_reg;
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90 | a_next = tmp1_reg + tmp2_reg;
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91 |
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92 | more_next = (d_reg > zero);
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93 | less_next = (d_reg < zero);
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94 |
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95 | /*
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96 | d_next = zero - (tap[index3])
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97 | - (tap[index2] << 1) - tap[index2]
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98 | + (tap[index1] << 1) + tap[index1]
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99 | + (tap[0]);
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100 |
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101 | a_next = (tap[index3])
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102 | + {tap[index2] << 1} + tap[index2]
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103 | + (tap[index1] << 1) + tap[index1]
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104 | + (tap[0]);
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105 | */
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106 | peak_next = (tap[peak_index] >> peak_shift);
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107 | end
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108 |
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109 | // output logic
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110 | assign d = d_reg;
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111 | assign a = a_reg;
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112 | assign peak = peak_reg;
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113 | assign flag = flag_reg;
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114 |
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115 | endmodule
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