[27] | 1 | module uwt_bior31
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| 2 | #(
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| 3 | parameter L = 1 // transform level
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| 4 | )
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| 5 | (
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| 6 | input wire clk, reset,
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| 7 | input wire [31:0] x,
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| 8 | output wire [31:0] d,
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| 9 | output wire [31:0] a,
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| 10 | output wire [31:0] peak,
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| 11 | output wire [1:0] flag
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| 12 | );
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| 13 |
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| 14 | localparam index1 = 1 << (L - 1);
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| 15 | localparam index2 = 2 << (L - 1);
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| 16 | localparam index3 = 3 << (L - 1);
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| 17 | localparam peak_index = ((3 << (L - 1)) + 1) >> 1;
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| 18 | localparam peak_shift = ((L - 1) << 1) + (L - 1);
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| 19 | localparam zero = 32'h80000000;
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| 20 |
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| 21 | // Tapped delay line
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| 22 | reg [31:0] tap [index3:0];
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| 23 |
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| 24 | reg [31:0] d_reg, d_next;
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| 25 | reg [31:0] a_reg, a_next;
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| 26 | reg [31:0] peak_reg, peak_next;
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| 27 |
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| 28 | reg [1:0] flag_reg;
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| 29 |
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| 30 | integer i;
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| 31 |
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| 32 | always @(posedge clk, posedge reset)
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| 33 | begin
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| 34 | if (reset)
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| 35 | begin
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| 36 | d_reg <= 0;
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| 37 | a_reg <= 0;
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| 38 | peak_reg <= 0;
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| 39 | flag_reg <= 0;
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| 40 |
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| 41 | for(i = 0; i <= index3; i = i + 1)
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| 42 | begin
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| 43 | tap[i] <= 0;
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| 44 | end
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| 45 | end
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| 46 | else
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| 47 | begin
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| 48 | d_reg <= d_next;
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| 49 | a_reg <= a_next;
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| 50 | peak_reg <= peak_next;
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| 51 |
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| 52 | flag_reg[0] <= (d_reg > zero) & (d_next <= zero);
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| 53 | flag_reg[1] <= (d_reg < zero) & (d_next >= zero);
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| 54 |
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| 55 | // Tapped delay line: shift one
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| 56 | for(i = 0; i < index3; i = i + 1)
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| 57 | begin
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| 58 | tap[i+1] <= tap[i];
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| 59 | end
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| 60 |
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| 61 | // Input in register 0
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| 62 | tap[0] <= x;
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| 63 | end
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| 64 | end
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| 65 |
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| 66 | always @*
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| 67 | begin
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| 68 | // Compute d and a with the filter coefficients.
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| 69 | // The coefficients are [1, 3, -3, -1] and [1, 3, 3, 1]
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| 70 |
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| 71 | d_next = zero - (tap[index3])
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| 72 | - (tap[index2] << 1) - tap[index2]
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| 73 | + (tap[index1] << 1) + tap[index1]
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| 74 | + (tap[0]);
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| 75 |
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| 76 | a_next = (tap[index3])
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| 77 | + (tap[index2] << 1) + tap[index2]
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| 78 | + (tap[index1] << 1) + tap[index1]
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| 79 | + (tap[0]);
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| 80 |
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| 81 | peak_next = (tap[peak_index] >> peak_shift);
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| 82 | end
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| 83 |
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| 84 | // output logic
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| 85 | assign d = d_reg;
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| 86 | assign a = a_reg;
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| 87 | assign peak = peak_reg;
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| 88 | assign flag = flag_reg;
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| 89 |
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| 90 | endmodule
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