Last change
on this file since 65 was 59, checked in by demin, 15 years ago |
move control and test code to separate modules
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File size:
793 bytes
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Rev | Line | |
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[59] | 1 | module test
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| 2 | (
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| 3 | input wire clk,
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| 4 | output wire tst_clk,
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| 5 | output wire [11:0] tst_data
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| 6 | );
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| 7 |
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| 8 | wire int_clk;
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| 9 | reg [11:0] int_data;
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| 10 | reg [2:0] state;
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| 11 |
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| 12 | test_pll test_pll_unit(
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| 13 | .inclk0(clk),
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| 14 | .c0(int_clk));
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| 15 |
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| 16 | always @(posedge int_clk)
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| 17 | begin
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| 18 | case (state)
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| 19 | 0:
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| 20 | begin
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| 21 | int_data <= 12'd0;
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| 22 | state <= 3'd1;
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| 23 | end
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| 24 |
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| 25 | 1:
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| 26 | begin
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| 27 | int_data <= 12'd1024;
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| 28 | state <= 3'd2;
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| 29 | end
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| 30 |
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| 31 | 2:
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| 32 | begin
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| 33 | int_data <= 12'd2048;
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| 34 | state <= 3'd3;
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| 35 | end
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| 36 |
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| 37 | 3:
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| 38 | begin
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| 39 | int_data <= 12'd3072;
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| 40 | state <= 3'd4;
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| 41 | end
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| 42 |
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| 43 | 4:
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| 44 | begin
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| 45 | int_data <= 12'd4095;
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| 46 | state <= 3'd0;
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| 47 | end
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| 48 |
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| 49 | default:
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| 50 | begin
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| 51 | state <= 3'd0;
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| 52 | end
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| 53 | endcase
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| 54 | end
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| 55 |
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| 56 | assign tst_clk = int_clk;
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| 57 | assign tst_data = int_data;
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| 58 |
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| 59 | endmodule
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