Last change
on this file since 89 was 84, checked in by demin, 15 years ago |
improve timings in all components
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File size:
376 bytes
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1 | module suppression
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2 | (
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3 | input wire clk,
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4 | input wire [11:0] data,
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5 | input wire [11:0] baseline,
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6 |
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7 | output wire [11:0] result
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8 | );
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9 |
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10 | reg [11:0] result_int;
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11 |
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12 | always @(posedge clk)
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13 | begin
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14 | if (data > baseline)
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15 | begin
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16 | result_int <= data - baseline;
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17 | end
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18 | else
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19 | begin
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20 | result_int <= 12'd0;
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21 | end
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22 | end
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23 |
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24 | assign result = result_int;
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25 | endmodule
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