| 1 | // megafunction wizard: %RAM: 2-PORT%
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| 2 | // GENERATION: STANDARD
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| 3 | // VERSION: WM1.0
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| 4 | // MODULE: altsyncram
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| 5 |
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| 6 | // ============================================================
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| 7 | // File Name: ram4096x24.v
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| 8 | // Megafunction Name(s):
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| 9 | // altsyncram
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| 10 | //
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| 11 | // Simulation Library Files(s):
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| 12 | // altera_mf
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| 13 | // ============================================================
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| 14 | // ************************************************************
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| 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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| 16 | //
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| 17 | // 9.0 Build 132 02/25/2009 SJ Web Edition
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| 18 | // ************************************************************
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| 19 |
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| 20 |
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| 21 | //Copyright (C) 1991-2009 Altera Corporation
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| 22 | //Your use of Altera Corporation's design tools, logic functions
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| 23 | //and other software and tools, and its AMPP partner logic
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| 24 | //functions, and any output files from any of the foregoing
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| 25 | //(including device programming or simulation files), and any
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| 26 | //associated documentation or information are expressly subject
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| 27 | //to the terms and conditions of the Altera Program License
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| 28 | //Subscription Agreement, Altera MegaCore Function License
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| 29 | //Agreement, or other applicable license agreement, including,
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| 30 | //without limitation, that your use is for the sole purpose of
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| 31 | //programming logic devices manufactured by Altera and sold by
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| 32 | //Altera or its authorized distributors. Please refer to the
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| 33 | //applicable agreement for further details.
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| 34 |
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| 35 |
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| 36 | // synopsys translate_off
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| 37 | `timescale 1 ps / 1 ps
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| 38 | // synopsys translate_on
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| 39 | module ram4096x24 (
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| 40 | address_a,
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| 41 | address_b,
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| 42 | clock,
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| 43 | data_a,
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| 44 | data_b,
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| 45 | wren_a,
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| 46 | wren_b,
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| 47 | q_a,
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| 48 | q_b);
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| 49 |
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| 50 | input [11:0] address_a;
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| 51 | input [11:0] address_b;
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| 52 | input clock;
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| 53 | input [23:0] data_a;
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| 54 | input [23:0] data_b;
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| 55 | input wren_a;
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| 56 | input wren_b;
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| 57 | output [23:0] q_a;
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| 58 | output [23:0] q_b;
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| 59 | `ifndef ALTERA_RESERVED_QIS
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| 60 | // synopsys translate_off
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| 61 | `endif
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| 62 | tri1 wren_a;
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| 63 | tri1 wren_b;
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| 64 | `ifndef ALTERA_RESERVED_QIS
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| 65 | // synopsys translate_on
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| 66 | `endif
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| 67 |
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| 68 | wire [23:0] sub_wire0;
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| 69 | wire [23:0] sub_wire1;
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| 70 | wire [23:0] q_a = sub_wire0[23:0];
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| 71 | wire [23:0] q_b = sub_wire1[23:0];
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| 72 |
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| 73 | altsyncram altsyncram_component (
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| 74 | .wren_a (wren_a),
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| 75 | .clock0 (clock),
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| 76 | .wren_b (wren_b),
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| 77 | .address_a (address_a),
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| 78 | .address_b (address_b),
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| 79 | .data_a (data_a),
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| 80 | .data_b (data_b),
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| 81 | .q_a (sub_wire0),
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| 82 | .q_b (sub_wire1),
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| 83 | .aclr0 (1'b0),
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| 84 | .aclr1 (1'b0),
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| 85 | .addressstall_a (1'b0),
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| 86 | .addressstall_b (1'b0),
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| 87 | .byteena_a (1'b1),
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| 88 | .byteena_b (1'b1),
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| 89 | .clock1 (1'b1),
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| 90 | .clocken0 (1'b1),
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| 91 | .clocken1 (1'b1),
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| 92 | .clocken2 (1'b1),
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| 93 | .clocken3 (1'b1),
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| 94 | .eccstatus (),
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| 95 | .rden_a (1'b1),
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| 96 | .rden_b (1'b1));
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| 97 | defparam
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| 98 | altsyncram_component.address_reg_b = "CLOCK0",
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| 99 | altsyncram_component.clock_enable_input_a = "BYPASS",
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| 100 | altsyncram_component.clock_enable_input_b = "BYPASS",
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| 101 | altsyncram_component.clock_enable_output_a = "BYPASS",
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| 102 | altsyncram_component.clock_enable_output_b = "BYPASS",
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| 103 | altsyncram_component.indata_reg_b = "CLOCK0",
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| 104 | altsyncram_component.intended_device_family = "Cyclone III",
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| 105 | altsyncram_component.lpm_type = "altsyncram",
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| 106 | altsyncram_component.numwords_a = 4096,
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| 107 | altsyncram_component.numwords_b = 4096,
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| 108 | altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
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| 109 | altsyncram_component.outdata_aclr_a = "NONE",
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| 110 | altsyncram_component.outdata_aclr_b = "NONE",
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| 111 | altsyncram_component.outdata_reg_a = "UNREGISTERED",
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| 112 | altsyncram_component.outdata_reg_b = "UNREGISTERED",
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| 113 | altsyncram_component.power_up_uninitialized = "FALSE",
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| 114 | altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
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| 115 | altsyncram_component.widthad_a = 12,
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| 116 | altsyncram_component.widthad_b = 12,
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| 117 | altsyncram_component.width_a = 24,
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| 118 | altsyncram_component.width_b = 24,
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| 119 | altsyncram_component.width_byteena_a = 1,
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| 120 | altsyncram_component.width_byteena_b = 1,
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| 121 | altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
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| 122 |
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| 123 |
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| 124 | endmodule
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