source: trunk/MultiChannelUSB/ram1024x16.v@ 41

// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram 

// ============================================================
// File Name: ram1024x16.v
// Megafunction Name(s):
//                      altsyncram
//
// Simulation Library Files(s):
//                      altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Web Edition
// ************************************************************


//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram1024x16 (
        clock,
        data,
        rdaddress,
        wraddress,
        wren,
        q);

        input     clock;
        input   [15:0]  data;
        input   [9:0]  rdaddress;
        input   [9:0]  wraddress;
        input     wren;
        output  [15:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
        tri1      wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

        wire [15:0] sub_wire0;
        wire [15:0] q = sub_wire0[15:0];

        altsyncram      altsyncram_component (
                                .wren_a (wren),
                                .clock0 (clock),
                                .address_a (wraddress),
                                .address_b (rdaddress),
                                .data_a (data),
                                .q_b (sub_wire0),
                                .aclr0 (1'b0),
                                .aclr1 (1'b0),
                                .addressstall_a (1'b0),
                                .addressstall_b (1'b0),
                                .byteena_a (1'b1),
                                .byteena_b (1'b1),
                                .clock1 (1'b1),
                                .clocken0 (1'b1),
                                .clocken1 (1'b1),
                                .clocken2 (1'b1),
                                .clocken3 (1'b1),
                                .data_b ({16{1'b1}}),
                                .eccstatus (),
                                .q_a (),
                                .rden_a (1'b1),
                                .rden_b (1'b1),
                                .wren_b (1'b0));
        defparam
                altsyncram_component.address_reg_b = "CLOCK0",
                altsyncram_component.clock_enable_input_a = "BYPASS",
                altsyncram_component.clock_enable_input_b = "BYPASS",
                altsyncram_component.clock_enable_output_a = "BYPASS",
                altsyncram_component.clock_enable_output_b = "BYPASS",
                altsyncram_component.intended_device_family = "Cyclone III",
                altsyncram_component.lpm_type = "altsyncram",
                altsyncram_component.numwords_a = 1024,
                altsyncram_component.numwords_b = 1024,
                altsyncram_component.operation_mode = "DUAL_PORT",
                altsyncram_component.outdata_aclr_b = "NONE",
                altsyncram_component.outdata_reg_b = "UNREGISTERED",
                altsyncram_component.power_up_uninitialized = "FALSE",
                altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
                altsyncram_component.widthad_a = 10,
                altsyncram_component.widthad_b = 10,
                altsyncram_component.width_a = 16,
                altsyncram_component.width_b = 16,
                altsyncram_component.width_byteena_a = 1;


endmodule