source: trunk/MultiChannelUSB/oscilloscope.v@ 28

Last change on this file since 28 was 27, checked in by demin, 15 years ago

initial commit

File size: 2.5 KB
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1module oscilloscope
2 (
3 input wire clk, reset,
4 input wire data_ready,
5 input wire [15:0] raw_data, uwt_data, threshold,
6 input wire [9:0] address,
7 output wire [9:0] start_address,
8 output wire [15:0] q
9 );
10
11 // signal declaration
12 reg [3:0] state_reg, state_next;
13
14 reg wren_reg, wren_next;
15 reg [9:0] addr_reg, addr_next;
16 reg [15:0] data_reg, data_next;
17
18 reg trig_reg, trig_next;
19 reg [9:0] trig_addr_reg, trig_addr_next;
20 reg [9:0] counter_reg, counter_next;
21
22 wire [15:0] q_wire;
23
24 ram1024x16 ram1024x16_unit (
25 .clock(~clk),
26 .data(data_reg),
27 .rdaddress(address),
28 .wraddress(addr_reg),
29 .wren(wren_reg),
30 .q(q_wire));
31
32 // body
33 always @(posedge clk)
34 begin
35 if (reset)
36 begin
37 state_reg <= 4'b1;
38 end
39 else
40 begin
41 state_reg <= state_next;
42 wren_reg <= wren_next;
43 addr_reg <= addr_next;
44 data_reg <= data_next;
45 trig_reg <= trig_next;
46 trig_addr_reg <= trig_addr_next;
47 counter_reg <= counter_next;
48 end
49 end
50
51 always @*
52 begin
53 state_next = state_reg;
54 wren_next = wren_reg;
55 addr_next = addr_reg;
56 data_next = data_reg;
57 trig_next = trig_reg;
58 trig_addr_next = trig_addr_reg;
59 counter_next = counter_reg;
60
61 case (state_reg)
62 0: ; // nothing to do
63 1:
64 begin
65 // start reset
66 wren_next = 1'b1;
67 addr_next = 0;
68 data_next = 0;
69 trig_next = 0;
70 trig_addr_next = 0;
71 counter_next = 0;
72 state_next = 4'd2;
73 end
74
75 2:
76 begin
77 // write zeros
78 if (&addr_reg)
79 begin
80 wren_next = 1'b0;
81 state_next = 4'd3;
82 end
83 else
84 begin
85 addr_next = addr_reg + 10'd1;
86 end
87 end
88
89 3:
90 begin
91 if (&counter_reg)
92 begin
93 state_next = 4'd0;
94 end
95 else if (data_ready)
96 begin
97 // start write
98 wren_next = 1'b1;
99 data_next = raw_data;
100 if ((~trig_reg)
101 & (counter_reg == 10'd512)
102 & (uwt_data >= threshold))
103 begin
104 // trigger
105 trig_next = 1'b1;
106 trig_addr_next = addr_reg;
107 end
108 state_next <= 4'd4;
109 end
110 end
111
112 4:
113 begin
114 // stop write
115 wren_next <= 1'b0;
116 addr_next = addr_reg + 10'd1;
117 if (trig_reg | (counter_reg < 10'd512))
118 begin
119 counter_next = counter_reg + 10'd1;
120 end
121 state_next = 4'd3;
122 end
123
124 default:
125 begin
126 state_next = 4'd0;
127 end
128 endcase
129 end
130
131 // output logic
132 assign q = q_wire;
133 assign start_address = trig_reg ? trig_addr_reg ^ 10'h200 : addr_reg + 10'd1;
134
135endmodule
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