source: trunk/MultiChannelUSB/oscilloscope.v@ 70

Last change on this file since 70 was 52, checked in by demin, 15 years ago

switch to normal memory clock

File size: 3.9 KB
Line 
1module oscilloscope
2 (
3 input wire clk, reset,
4 input wire data_ready,
5 input wire [15:0] raw_data, uwt_data, threshold,
6 input wire [9:0] address,
7 output wire [9:0] start_address,
8 output wire [15:0] q
9 );
10
11 // signal declaration
12 reg [3:0] state_reg, state_next;
13 reg flag_reg, flag_next;
14 reg wren_reg, wren_next;
15 reg [9:0] addr_reg, addr_next;
16 reg [15:0] data_reg, data_next;
17
18 reg trig_reg, trig_next;
19 reg [9:0] trig_addr_reg, trig_addr_next;
20 reg [9:0] counter_reg, counter_next;
21
22 wire [15:0] q_wire;
23
24 wire [15:0] data_wire;
25
26 assign data_wire = (flag_reg) ? raw_data : data_reg;
27
28 altsyncram #(
29 .address_reg_b("CLOCK0"),
30 .clock_enable_input_a("BYPASS"),
31 .clock_enable_input_b("BYPASS"),
32 .clock_enable_output_a("BYPASS"),
33 .clock_enable_output_b("BYPASS"),
34 .intended_device_family("Cyclone III"),
35 .lpm_type("altsyncram"),
36 .numwords_a(1024),
37 .numwords_b(1024),
38 .operation_mode("DUAL_PORT"),
39 .outdata_aclr_b("NONE"),
40 .outdata_reg_b("UNREGISTERED"),
41 .power_up_uninitialized("FALSE"),
42 .read_during_write_mode_mixed_ports("OLD_DATA"),
43 .widthad_a(10),
44 .widthad_b(10),
45 .width_a(16),
46 .width_b(16),
47 .width_byteena_a(1)) osc_ram_unit(
48 .wren_a(wren_reg),
49 .clock0(clk),
50 .address_a(addr_reg),
51 .address_b(address),
52 .data_a(data_wire),
53 .q_b(q_wire),
54 .aclr0(1'b0),
55 .aclr1(1'b0),
56 .addressstall_a(1'b0),
57 .addressstall_b(1'b0),
58 .byteena_a(1'b1),
59 .byteena_b(1'b1),
60 .clock1(1'b1),
61 .clocken0(1'b1),
62 .clocken1(1'b1),
63 .clocken2(1'b1),
64 .clocken3(1'b1),
65 .data_b({16{1'b1}}),
66 .eccstatus(),
67 .q_a(),
68 .rden_a(1'b1),
69 .rden_b(1'b1),
70 .wren_b(1'b0));
71
72 // body
73 always @(posedge clk)
74 begin
75 if (reset)
76 begin
77 state_reg <= 4'b1;
78 flag_reg <= 1'b0;
79 wren_reg <= 1'b1;
80 addr_reg <= 10'd0;
81 data_reg <= 16'd0;
82 trig_reg <= 1'b0;
83 trig_addr_reg <= 10'd0;
84 counter_reg <= 10'd0;
85 end
86 else
87 begin
88 state_reg <= state_next;
89 flag_reg <= flag_next;
90 wren_reg <= wren_next;
91 addr_reg <= addr_next;
92 data_reg <= data_next;
93 trig_reg <= trig_next;
94 trig_addr_reg <= trig_addr_next;
95 counter_reg <= counter_next;
96 end
97 end
98
99 always @*
100 begin
101 state_next = state_reg;
102 flag_next = flag_reg;
103 wren_next = wren_reg;
104 addr_next = addr_reg;
105 data_next = data_reg;
106 trig_next = trig_reg;
107 trig_addr_next = trig_addr_reg;
108 counter_next = counter_reg;
109
110 case (state_reg)
111 0:
112 begin
113 // nothing to do
114 state_next = 4'b0;
115 flag_next = 1'b0;
116 wren_next = 1'b0;
117 addr_next = 10'd0;
118 data_next = 16'd0;
119 counter_next = 10'd0;
120 end
121
122 1:
123 begin
124 // write zeros
125 if (&addr_reg)
126 begin
127 flag_next = 1'b1;
128 wren_next = 1'b0;
129 state_next = 4'd2;
130 end
131 else
132 begin
133 addr_next = addr_reg + 10'd1;
134 end
135 end
136
137 2:
138 begin
139 if (data_ready)
140 begin
141 wren_next = 1'b1;
142 state_next = 4'd3;
143 end
144 end
145
146 3:
147 begin
148 // stop write
149 wren_next = 1'b0;
150 addr_next = addr_reg + 10'd1;
151
152 if (&counter_reg)
153 begin
154 flag_next = 1'b0;
155 state_next = 4'd0;
156 end
157 else
158 begin
159 state_next = 4'd2;
160
161 if ((~trig_reg)
162 & (counter_reg == 10'd512)
163 & (uwt_data >= threshold))
164 begin
165 // trigger
166 trig_next = 1'b1;
167 trig_addr_next = addr_reg;
168 end
169
170 if (trig_reg | (counter_reg < 10'd512))
171 begin
172 counter_next = counter_reg + 10'd1;
173 end
174 end
175 end
176
177 default:
178 begin
179 state_next = 4'b0;
180 flag_next = 1'b0;
181 wren_next = 1'b0;
182 addr_next = 10'd0;
183 data_next = 16'd0;
184 counter_next = 10'd0;
185 end
186 endcase
187 end
188
189 // output logic
190 assign q = q_wire;
191 assign start_address = trig_reg ? (trig_addr_reg ^ 10'h200) + 10'd1: addr_reg + 10'd1;
192
193endmodule
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