source: trunk/MultiChannelUSB/i2c_fifo.v@ 77

Last change on this file since 77 was 71, checked in by demin, 15 years ago

move to central clock domain

  • Property svn:executable set to *
File size: 3.1 KB
Line 
1module i2c_fifo
2 (
3 input wire clk, aclr,
4 input wire wrreq,
5 input wire [15:0] data,
6 output wire full,
7
8 inout wire i2c_sda,
9 inout wire i2c_scl
10 );
11
12 wire int_rdempty, i2c_clk, start, stop;
13 wire [15:0] int_q;
14
15 reg int_rdreq, int_clken, int_sdo, int_scl, int_ack;
16 reg [15:0] int_data;
17 reg [8:0] counter;
18 reg [4:0] state;
19
20 assign i2c_sda = int_sdo ? 1'bz : 1'b0;
21 assign i2c_scl = int_scl | (int_clken ? counter[8] : 1'b0);
22
23 assign start = int_data[8];
24 assign stop = int_data[9];
25
26 scfifo #(
27 .add_ram_output_register("OFF"),
28 .intended_device_family("Cyclone III"),
29 .lpm_numwords(16),
30 .lpm_showahead("ON"),
31 .lpm_type("scfifo"),
32 .lpm_width(16),
33 .lpm_widthu(4),
34 .overflow_checking("ON"),
35 .underflow_checking("ON"),
36 .use_eab("OFF")) fifo_tx (
37 .rdreq((~int_rdempty) & (int_rdreq) & (&counter)),
38 .aclr(aclr),
39 .clock(clk),
40 .wrreq(wrreq),
41 .data(data),
42 .empty(int_rdempty),
43 .q(int_q),
44 .full(full),
45 .almost_empty(),
46 .almost_full(),
47 .sclr(),
48 .usedw());
49
50 always @ (posedge clk)
51 begin
52 counter <= counter + 9'd1;
53 if (&counter)
54 begin
55 case (state)
56 0:
57 begin
58 int_ack <= 1'b0;
59 int_sdo <= 1'b1;
60 int_scl <= 1'b1;
61 int_rdreq <= 1'b1;
62 state <= 5'd1;
63 end
64
65 1:
66 begin
67 if (~int_rdempty)
68 begin
69 int_data <= int_q;
70 int_rdreq <= 1'b0;
71 state <= 5'd2;
72 end
73 end
74
75 2:
76 begin
77 if (start)
78 begin
79 int_sdo <= 1'b1;
80 int_scl <= 1'b1;
81 state <= 5'd3;
82 end
83 else
84 begin
85 state <= 5'd5;
86 end
87 end
88
89 3:
90 begin // start
91 int_sdo <= 1'b0;
92 state <= 5'd4;
93 end
94
95 4:
96 begin
97 int_scl <= 1'b0;
98 state <= 5'd5;
99 end
100
101 5:
102 begin // data
103 int_clken <= 1'b1;
104 int_sdo <= int_data[7];
105 state <= 5'd6;
106 end
107
108 6:
109 begin
110 int_sdo <= int_data[6];
111 state <= 5'd7;
112 end
113
114 7:
115 begin
116 int_sdo <= int_data[5];
117 state <= 5'd8;
118 end
119
120 8:
121 begin
122 int_sdo <= int_data[4];
123 state <= 5'd9;
124 end
125
126 9:
127 begin
128 int_sdo <= int_data[3];
129 state <= 5'd10;
130 end
131
132 10:
133 begin
134 int_sdo <= int_data[2];
135 state <= 5'd11;
136 end
137
138 11:
139 begin
140 int_sdo <= int_data[1];
141 state <= 5'd12;
142 end
143
144 12:
145 begin
146 int_sdo <= int_data[0];
147 state <= 5'd13;
148 end
149
150 13:
151 begin // ack
152 int_sdo <= 1'b1;
153 int_rdreq <= 1'b1;
154 state <= 5'd14;
155 end
156
157 14:
158 begin
159 int_ack <= i2c_sda;
160 int_rdreq <= 1'b0;
161 if (stop | int_rdempty)
162 begin
163 int_clken <= 1'b0;
164 int_sdo <= 1'b0;
165 int_scl <= 1'b0;
166 state <= 5'd15;
167 end
168 else if (~int_rdempty)
169 begin
170 int_data <= int_q;
171 int_sdo <= int_q[7];
172 state <= 5'd6;
173 end
174 end
175
176 15:
177 begin // stop
178 int_scl <= 1'b1;
179 state <= 5'd16;
180 end
181
182 16:
183 begin
184 int_sdo <= 1'b1;
185 state <= 5'd0;
186 end
187
188 endcase
189 end
190 end
191
192endmodule
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