source: trunk/MultiChannelUSB/i2c_fifo.v@ 70

Last change on this file since 70 was 70, checked in by demin, 15 years ago

intermediate working version with 32 bit histograms, test block and I2C master
  • Property svn:executable set to *
File size: 3.1 KB
Line 
1module i2c_fifo
2 (
3 input wire clk, aclr,
4 input wire wrreq,
5 input wire [15:0] data,
6 output wire full,
7
8 inout wire i2c_sda,
9 output wire i2c_scl
10 );
11
12 wire int_rdempty, i2c_clk, start, stop;
13 wire [15:0] int_q;
14
15 reg int_rdreq, int_clken, int_sdo, int_scl, int_ack;
16 reg [15:0] int_data;
17 reg [8:0] counter;
18 reg [4:0] state;
19
20 assign i2c_clk = counter[8];
21
22 assign i2c_sda = int_sdo ? 1'bz : 1'b0;
23 assign i2c_scl = int_scl | (int_clken ? ~i2c_clk : 1'b0);
24
25 assign start = int_data[8];
26 assign stop = int_data[9];
27
28 dcfifo #(
29 .intended_device_family("Cyclone III"),
30 .lpm_numwords(16),
31 .lpm_showahead("ON"),
32 .lpm_type("dcfifo"),
33 .lpm_width(16),
34 .lpm_widthu(4),
35 .rdsync_delaypipe(4),
36 .wrsync_delaypipe(4),
37 .overflow_checking("ON"),
38 .underflow_checking("ON"),
39 .use_eab("OFF"),
40 .write_aclr_synch("OFF")) fifo_tx (
41 .aclr(aclr),
42 .data(data),
43 .rdclk(i2c_clk),
44 .rdreq((~int_rdempty) & int_rdreq),
45 .wrclk(clk),
46 .wrreq(wrreq),
47 .q(int_q),
48 .rdempty(int_rdempty),
49 .wrfull(full),
50 .rdfull(),
51 .rdusedw(),
52 .wrempty(),
53 .wrusedw());
54
55 always @ (posedge clk)
56 begin
57 counter <= counter + 9'd1;
58 end
59
60 always @ (posedge i2c_clk)
61 begin
62 case (state)
63 0:
64 begin
65 int_ack <= 1'b0;
66 int_sdo <= 1'b1;
67 int_scl <= 1'b1;
68 int_rdreq <= 1'b1;
69 state <= 5'd1;
70 end
71
72 1:
73 begin
74 if (~int_rdempty)
75 begin
76 int_data <= int_q;
77 int_rdreq <= 1'b0;
78 state <= 5'd2;
79 end
80 end
81
82 2:
83 begin
84 if (start)
85 begin
86 int_sdo <= 1'b1;
87 int_scl <= 1'b1;
88 state <= 5'd3;
89 end
90 else
91 begin
92 state <= 5'd5;
93 end
94 end
95
96 3:
97 begin // start
98 int_sdo <= 1'b0;
99 state <= 5'd4;
100 end
101
102 4:
103 begin
104 int_scl <= 1'b0;
105 state <= 5'd5;
106 end
107
108 5:
109 begin // data
110 int_clken <= 1'b1;
111 int_sdo <= int_data[7];
112 state <= 5'd6;
113 end
114
115 6:
116 begin
117 int_sdo <= int_data[6];
118 state <= 5'd7;
119 end
120
121 7:
122 begin
123 int_sdo <= int_data[5];
124 state <= 5'd8;
125 end
126
127 8:
128 begin
129 int_sdo <= int_data[4];
130 state <= 5'd9;
131 end
132
133 9:
134 begin
135 int_sdo <= int_data[3];
136 state <= 5'd10;
137 end
138
139 10:
140 begin
141 int_sdo <= int_data[2];
142 state <= 5'd11;
143 end
144
145 11:
146 begin
147 int_sdo <= int_data[1];
148 state <= 5'd12;
149 end
150
151 12:
152 begin
153 int_sdo <= int_data[0];
154 state <= 5'd13;
155 end
156
157 13:
158 begin // ack
159 int_sdo <= 1'b1;
160 int_rdreq <= 1'b1;
161 state <= 5'd14;
162 end
163
164 14:
165 begin
166 int_ack <= i2c_sda;
167 int_rdreq <= 1'b0;
168 if (stop | int_rdempty)
169 begin
170 int_clken <= 1'b0;
171 int_sdo <= 1'b0;
172 int_scl <= 1'b0;
173 state <= 5'd15;
174 end
175 else if (~int_rdempty)
176 begin
177 int_data <= int_q;
178 int_sdo <= int_q[7];
179 state <= 5'd6;
180 end
181 end
182
183 15:
184 begin // stop
185 int_scl <= 1'b1;
186 state <= 5'd16;
187 end
188
189 16:
190 begin
191 int_sdo <= 1'b1;
192 state <= 5'd0;
193 end
194
195 endcase
196 end
197
198endmodule
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