source: trunk/MultiChannelUSB/histogram.v@ 33

Last change on this file since 33 was 27, checked in by demin, 15 years ago

initial commit

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1module histogram
2 (
3 input wire clk, reset,
4 input wire data_ready,
5 input wire [11:0] data, address,
6 output wire [31:0] q
7 );
8
9 // signal declaration
10 reg [3:0] state_reg, state_next;
11 reg wren_reg, wren_next;
12 reg [11:0] addr_reg, addr_next;
13 reg [31:0] data_reg, data_next;
14
15 wire [31:0] q_a_wire, q_b_wire;
16
17 ram4096x32 ram4096x32_unit (
18 .address_a(addr_reg),
19 .address_b(address),
20 .clock(~clk),
21 .data_a(data_reg),
22 .data_b(),
23 .wren_a(wren_reg),
24 .wren_b(1'b0),
25 .q_a(q_a_wire),
26 .q_b(q_b_wire));
27
28 // body
29 always @(posedge clk)
30 begin
31 if (reset)
32 begin
33 state_reg <= 4'b1;
34 end
35 else
36 begin
37 state_reg <= state_next;
38 wren_reg <= wren_next;
39 addr_reg <= addr_next;
40 data_reg <= data_next;
41 end
42 end
43
44 always @*
45 begin
46 state_next = state_reg;
47 wren_next = wren_reg;
48 addr_next = addr_reg;
49 data_next = data_reg;
50 case (state_reg)
51 0: ; // nothing to do
52 1:
53 begin
54 // start reset
55 wren_next = 1'b1;
56 addr_next = 0;
57 data_next = 0;
58 state_next = 4'd2;
59 end
60
61 2:
62 begin
63 // write zeros
64 if (&addr_reg)
65 begin
66 state_next = 4'd3;
67 end
68 else
69 begin
70 addr_next = addr_reg + 12'd1;
71 end
72 end
73
74 3:
75 begin
76 // read
77 wren_next = 1'b0;
78 if (&data_reg)
79 begin
80 state_next = 4'd0;
81 end
82 else if (data_ready)
83 begin
84 // set addr
85 addr_next = data;
86 state_next = 4'd4;
87 end
88 end
89
90 4:
91 begin
92 // increment and write
93 wren_next = 1'b1;
94 data_next = q_a_wire + 32'd1;
95 state_next = 4'd3;
96 end
97
98 default:
99 begin
100 state_next = 4'd0;
101 end
102 endcase
103 end
104
105 // output logic
106 assign q = q_b_wire;
107endmodule
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