source: trunk/MultiChannelUSB/histogram.v@ 55

Last change on this file since 55 was 52, checked in by demin, 15 years ago

switch to normal memory clock

File size: 3.2 KB
Line 
1module histogram
2 (
3 input wire clk, reset,
4 input wire data_ready,
5 input wire [11:0] data, address,
6 output wire [23:0] q
7 );
8
9 // signal declaration
10 reg [3:0] state_reg, state_next;
11 reg flag_reg, flag_next;
12 reg wren_reg, wren_next;
13 reg [11:0] addr_reg, addr_next;
14 reg [23:0] data_reg, data_next;
15
16 wire [23:0] q_a_wire, q_b_wire;
17
18 wire [11:0] addr_wire;
19 wire [23:0] data_wire;
20
21 assign addr_wire = (flag_reg) ? data : addr_reg;
22 assign data_wire = (flag_reg) ? (q_a_wire + 24'd1) : data_reg;
23
24 altsyncram #(
25 .address_reg_b("CLOCK0"),
26 .clock_enable_input_a("BYPASS"),
27 .clock_enable_input_b("BYPASS"),
28 .clock_enable_output_a("BYPASS"),
29 .clock_enable_output_b("BYPASS"),
30 .indata_reg_b("CLOCK0"),
31 .intended_device_family("Cyclone III"),
32 .lpm_type("altsyncram"),
33 .numwords_a(4096),
34 .numwords_b(4096),
35 .operation_mode("BIDIR_DUAL_PORT"),
36 .outdata_aclr_a("NONE"),
37 .outdata_aclr_b("NONE"),
38 .outdata_reg_a("UNREGISTERED"),
39 .outdata_reg_b("UNREGISTERED"),
40 .power_up_uninitialized("FALSE"),
41 .read_during_write_mode_mixed_ports("OLD_DATA"),
42 .widthad_a(12),
43 .widthad_b(12),
44 .width_a(24),
45 .width_b(24),
46 .width_byteena_a(1),
47 .width_byteena_b(1),
48 .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit(
49 .wren_a(wren_reg),
50 .clock0(clk),
51 .wren_b(1'b0),
52 .address_a(addr_wire),
53 .address_b(address),
54 .data_a(data_wire),
55 .data_b(),
56 .q_a(q_a_wire),
57 .q_b(q_b_wire),
58 .aclr0(1'b0),
59 .aclr1(1'b0),
60 .addressstall_a(1'b0),
61 .addressstall_b(1'b0),
62 .byteena_a(1'b1),
63 .byteena_b(1'b1),
64 .clock1(1'b1),
65 .clocken0(1'b1),
66 .clocken1(1'b1),
67 .clocken2(1'b1),
68 .clocken3(1'b1),
69 .eccstatus(),
70 .rden_a(1'b1),
71 .rden_b(1'b1));
72
73 // body
74 always @(posedge clk)
75 begin
76 if (reset)
77 begin
78 flag_reg <= 1'b0;
79 wren_reg <= 1'b1;
80 addr_reg <= 12'd0;
81 data_reg <= 24'd0;
82 state_reg <= 4'b1;
83 end
84 else
85 begin
86 flag_reg <= flag_next;
87 wren_reg <= wren_next;
88 addr_reg <= addr_next;
89 data_reg <= data_next;
90 state_reg <= state_next;
91 end
92 end
93
94 always @*
95 begin
96 flag_next = flag_reg;
97 wren_next = wren_reg;
98 addr_next = addr_reg;
99 data_next = data_reg;
100 state_next = state_reg;
101 case (state_reg)
102 0:
103 begin
104 // nothing to do
105 flag_next = 1'b0;
106 wren_next = 1'b0;
107 addr_next = 12'd0;
108 data_next = 24'd0;
109 state_next = 4'd0;
110 end
111
112 1:
113 begin
114 // write zeros
115 if (&addr_reg)
116 begin
117 flag_next = 1'b1;
118 wren_next = 1'b0;
119 state_next = 4'd2;
120 end
121 else
122 begin
123 addr_next = addr_reg + 12'd1;
124 end
125 end
126
127 2:
128 begin
129 if (data_ready)
130 begin
131 if (&q_a_wire)
132 begin
133 flag_next = 1'b0;
134 state_next = 4'd0;
135 end
136 else
137 begin
138 wren_next = 1'b1;
139 state_next = 4'd3;
140 end
141 end
142 end
143
144 3:
145 begin
146 wren_next = 1'b0;
147 state_next = 4'd2;
148 end
149
150 default:
151 begin
152 flag_next = 1'b0;
153 wren_next = 1'b0;
154 addr_next = 12'd0;
155 data_next = 24'd0;
156 state_next = 4'd0;
157 end
158 endcase
159 end
160
161 // output logic
162 assign q = q_b_wire;
163endmodule
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