source: trunk/MultiChannelUSB/histogram.v@ 48

Last change on this file since 48 was 47, checked in by demin, 15 years ago

switch to direct instantiation of altsyncram

File size: 2.8 KB
Line 
1module histogram
2 (
3 input wire clk, reset,
4 input wire data_ready,
5 input wire [11:0] data, address,
6 output wire [23:0] q
7 );
8
9 // signal declaration
10 reg [3:0] state_reg, state_next;
11 reg wren_reg, wren_next;
12 reg [11:0] addr_reg, addr_next;
13 reg [23:0] data_reg, data_next;
14
15 wire [23:0] q_a_wire, q_b_wire;
16
17 altsyncram #(
18 .address_reg_b("CLOCK0"),
19 .clock_enable_input_a("BYPASS"),
20 .clock_enable_input_b("BYPASS"),
21 .clock_enable_output_a("BYPASS"),
22 .clock_enable_output_b("BYPASS"),
23 .indata_reg_b("CLOCK0"),
24 .intended_device_family("Cyclone III"),
25 .lpm_type("altsyncram"),
26 .numwords_a(4096),
27 .numwords_b(4096),
28 .operation_mode("BIDIR_DUAL_PORT"),
29 .outdata_aclr_a("NONE"),
30 .outdata_aclr_b("NONE"),
31 .outdata_reg_a("UNREGISTERED"),
32 .outdata_reg_b("UNREGISTERED"),
33 .power_up_uninitialized("FALSE"),
34 .read_during_write_mode_mixed_ports("OLD_DATA"),
35 .widthad_a(12),
36 .widthad_b(12),
37 .width_a(24),
38 .width_b(24),
39 .width_byteena_a(1),
40 .width_byteena_b(1),
41 .wrcontrol_wraddress_reg_b("CLOCK0")) hst_ram_unit (
42 .wren_a (wren_reg),
43 .clock0 (~clk),
44 .wren_b (1'b0),
45 .address_a (addr_reg),
46 .address_b (address),
47 .data_a (data_reg),
48 .data_b (),
49 .q_a (q_a_wire),
50 .q_b (q_b_wire),
51 .aclr0 (1'b0),
52 .aclr1 (1'b0),
53 .addressstall_a (1'b0),
54 .addressstall_b (1'b0),
55 .byteena_a (1'b1),
56 .byteena_b (1'b1),
57 .clock1 (1'b1),
58 .clocken0 (1'b1),
59 .clocken1 (1'b1),
60 .clocken2 (1'b1),
61 .clocken3 (1'b1),
62 .eccstatus (),
63 .rden_a (1'b1),
64 .rden_b (1'b1));
65
66 // body
67 always @(posedge clk)
68 begin
69 if (reset)
70 begin
71 state_reg <= 4'b1;
72 end
73 else
74 begin
75 state_reg <= state_next;
76 wren_reg <= wren_next;
77 addr_reg <= addr_next;
78 data_reg <= data_next;
79 end
80 end
81
82 always @*
83 begin
84 state_next = state_reg;
85 wren_next = wren_reg;
86 addr_next = addr_reg;
87 data_next = data_reg;
88 case (state_reg)
89 0: ; // nothing to do
90 1:
91 begin
92 // start reset
93 wren_next = 1'b1;
94 addr_next = 0;
95 data_next = 0;
96 state_next = 4'd2;
97 end
98
99 2:
100 begin
101 // write zeros
102 if (&addr_reg)
103 begin
104 state_next = 4'd3;
105 end
106 else
107 begin
108 addr_next = addr_reg + 12'd1;
109 end
110 end
111
112 3:
113 begin
114 // read
115 wren_next = 1'b0;
116 if (&data_reg)
117 begin
118 state_next = 4'd0;
119 end
120 else if (data_ready)
121 begin
122 // set addr
123 addr_next = data;
124 state_next = 4'd4;
125 end
126 end
127
128 4:
129 begin
130 // increment and write
131 wren_next = 1'b1;
132 data_next = q_a_wire + 24'd1;
133 state_next = 4'd3;
134 end
135
136 default:
137 begin
138 state_next = 4'd0;
139 end
140 endcase
141 end
142
143 // output logic
144 assign q = q_b_wire;
145endmodule
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