source: trunk/MultiChannelUSB/fifo32x12.v@ 41

// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo 

// ============================================================
// File Name: fifo32x12.v
// Megafunction Name(s):
//                      dcfifo
//
// Simulation Library Files(s):
//                      altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Web Edition
// ************************************************************


//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo32x12 (
        aclr,
        data,
        rdclk,
        rdreq,
        wrclk,
        wrreq,
        q,
        rdempty,
        wrfull);

        input     aclr;
        input   [11:0]  data;
        input     rdclk;
        input     rdreq;
        input     wrclk;
        input     wrreq;
        output  [11:0]  q;
        output    rdempty;
        output    wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
        tri0      aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

        wire  sub_wire0;
        wire  sub_wire1;
        wire [11:0] sub_wire2;
        wire  rdempty = sub_wire0;
        wire  wrfull = sub_wire1;
        wire [11:0] q = sub_wire2[11:0];

        dcfifo  dcfifo_component (
                                .wrclk (wrclk),
                                .rdreq (rdreq),
                                .aclr (aclr),
                                .rdclk (rdclk),
                                .wrreq (wrreq),
                                .data (data),
                                .rdempty (sub_wire0),
                                .wrfull (sub_wire1),
                                .q (sub_wire2)
                                // synopsys translate_off
                                ,
                                .rdfull (),
                                .rdusedw (),
                                .wrempty (),
                                .wrusedw ()
                                // synopsys translate_on
                                );
        defparam
                dcfifo_component.intended_device_family = "Cyclone III",
                dcfifo_component.lpm_numwords = 32,
                dcfifo_component.lpm_showahead = "ON",
                dcfifo_component.lpm_type = "dcfifo",
                dcfifo_component.lpm_width = 12,
                dcfifo_component.lpm_widthu = 5,
                dcfifo_component.overflow_checking = "ON",
                dcfifo_component.rdsync_delaypipe = 4,
                dcfifo_component.underflow_checking = "ON",
                dcfifo_component.use_eab = "ON",
                dcfifo_component.write_aclr_synch = "OFF",
                dcfifo_component.wrsync_delaypipe = 4;


endmodule