source: trunk/MultiChannelUSB/counter.v@ 180

Last change on this file since 180 was 159, checked in by demin, 13 years ago

adapt to paella v2

File size: 1.9 KB
Line 
1module counter
2 (
3 input wire clock, frame,
4
5 input wire reset, setup, count,
6
7 input wire bus_ssel, bus_wren,
8 input wire [1:0] bus_addr,
9 input wire [15:0] bus_mosi,
10
11 output wire [15:0] bus_miso,
12 output wire bus_busy,
13
14 output wire cnt_good
15 );
16
17 wire [3:0] int_ssel_wire;
18 wire [15:0] int_miso_wire;
19
20 reg cnt_good_reg;
21 reg [15:0] int_miso_reg;
22
23 wire [63:0] reg_bits_wire;
24 wire [63:0] cnt_bits_wire;
25
26 reg int_load_reg;
27
28 integer i;
29 genvar j;
30
31 lpm_counter #(
32 .lpm_direction("DOWN"),
33 .lpm_port_updown("PORT_UNUSED"),
34 .lpm_type("LPM_COUNTER"),
35 .lpm_width(64)) lpm_counter_component (
36 .sload(int_load_reg | setup),
37 .sclr(reset),
38 .clock(clock),
39 .data(reg_bits_wire),
40 .cnt_en((frame) & (count) & (|cnt_bits_wire)),
41 .q(cnt_bits_wire));
42
43 generate
44 for (j = 0; j < 4; j = j + 1)
45 begin : BUS_OUTPUT
46 lpm_ff #(
47 .lpm_fftype("DFF"),
48 .lpm_type("LPM_FF"),
49 .lpm_width(16)) cfg_reg_unit (
50 .enable(int_ssel_wire[j] & bus_ssel & bus_wren),
51 .sclr(reset),
52 .clock(clock),
53 .data(bus_mosi),
54 .q(reg_bits_wire[j*16+15:j*16]));
55 end
56 endgenerate
57
58 lpm_mux #(
59 .lpm_size(4),
60 .lpm_type("LPM_MUX"),
61 .lpm_width(16),
62 .lpm_widths(2)) bus_miso_mux_unit (
63 .sel(bus_addr),
64 .data(cnt_bits_wire),
65 .result(int_miso_wire));
66
67
68 lpm_decode #(
69 .lpm_decodes(4),
70 .lpm_type("LPM_DECODE"),
71 .lpm_width(2)) lpm_decode_unit (
72 .data(bus_addr),
73 .eq(int_ssel_wire));
74
75 always @(posedge clock)
76 begin
77 if (reset)
78 begin
79 int_miso_reg <= 16'd0;
80 cnt_good_reg <= 1'b0;
81 int_load_reg <= 1'b0;
82 end
83 else
84 begin
85 int_miso_reg <= int_miso_wire;
86 cnt_good_reg <= |cnt_bits_wire;
87 int_load_reg <= bus_ssel & bus_wren;
88 end
89 end
90
91 // output logic
92 assign bus_miso = int_miso_reg;
93 assign bus_busy = 1'b0;
94 assign cnt_good = cnt_good_reg;
95
96endmodule
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