source: trunk/MultiChannelUSB/control.v@ 66

Last change on this file since 66 was 65, checked in by demin, 15 years ago

start testing SRAM
File size: 6.0 KB
Line 
1module control
2 (
3 input wire clk,
4 input wire rx_empty, tx_full,
5 input wire [7:0] rx_data,
6 input wire [1:0] mux_max_byte,
7 input wire [15:0] mux_min_addr, mux_max_addr,
8 input wire [7:0] mux_q,
9
10 output wire mux_reset,
11 output wire mux_type,
12 output wire [1:0] mux_chan,
13 output wire [1:0] mux_byte,
14 output wire [15:0] mux_addr,
15 output wire rx_rdreq,
16 output wire tx_wrreq,
17 output wire [7:0] tx_data,
18 output wire ram_we,
19 output wire [19:0] ram_addr,
20 inout wire [17:0] ram_data,
21 output wire led
22 );
23
24 reg [23:0] led_counter;
25 reg [18:0] ram_counter;
26 reg [10:0] tst_counter;
27 reg [15:0] int_addr, int_max_addr;
28
29 reg int_rdreq, int_wrreq;
30 reg int_type, int_reset;
31 reg [1:0] int_chan, int_byte, int_max_byte;
32 reg [7:0] int_data;
33 reg int_led;
34
35
36 wire crc_error = 1'b0;
37 reg crc_reset;
38 reg [2:0] byte_counter;
39 reg [4:0] idle_counter;
40
41 reg [3:0] state;
42
43 wire [15:0] src, dst;
44
45 reg [15:0] memory [15:0];
46 reg [7:0] buffer [7:0];
47
48 assign src = (buffer[0][7]) ? memory[buffer[3][3:0]] : {buffer[2], buffer[3]};
49 assign dst = {1'b0, buffer[0][6:0], buffer[1]};
50
51 reg int_ram_we;
52 reg [17:0] int_ram_data;
53 wire [17:0] int_ram_q;
54 wire [17:0] opt_ram_we;
55 assign ram_we = ~int_ram_we;
56 assign int_ram_q = ram_data;
57// assign ram_data = int_ram_we ? int_ram_data : 18'bz;
58 assign ram_addr = {ram_counter[18:5],1'd0,ram_counter[4:0]};
59
60 genvar j;
61 generate
62 for (j = 0; j < 18; j = j + 1)
63 begin : SRAM_WE
64 assign opt_ram_we[j] = int_ram_we;
65 assign ram_data[j] = opt_ram_we[j] ? int_ram_data[j] : 1'bz;
66 end
67 endgenerate
68
69 always @(posedge clk)
70 begin
71 if (~rx_empty)
72 begin
73 int_led <= 1'b0;
74 led_counter <= 24'd0;
75 end
76 else
77 begin
78 if (&led_counter)
79 begin
80 int_led <= 1'b1;
81 end
82 else
83 begin
84 led_counter <= led_counter + 24'd1;
85 end
86 end
87
88 case(state)
89 0:
90 begin
91 int_rdreq <= 1'b1;
92 int_wrreq <= 1'b0;
93 int_type <= 1'b0;
94 int_chan <= 2'd0;
95 int_byte <= 2'd0;
96 int_reset <= 1'b0;
97 crc_reset <= 1'b0;
98 int_ram_we <= 1'b0;
99 int_ram_data <= 16'd0;
100 ram_counter <= 19'd0;
101 idle_counter <= 5'd0;
102 byte_counter <= 3'd0;
103 state <= 4'd1;
104 end
105
106 1:
107 begin
108 // read 8 bytes
109 if (~rx_empty)
110 begin
111 idle_counter <= 5'd0;
112 byte_counter <= byte_counter + 3'd1;
113 buffer[byte_counter] <= rx_data;
114 if (&byte_counter)
115 begin
116 int_rdreq <= 1'b0;
117 state <= 4'd2;
118 end
119 end
120 else if(|byte_counter)
121 begin
122 idle_counter <= idle_counter + 5'd1;
123 if (&idle_counter)
124 begin
125 int_rdreq <= 1'b0;
126 crc_reset <= 1'b1;
127 state <= 4'd0;
128 end
129 end
130 end
131
132 2:
133 begin
134 crc_reset <= 1'b1;
135 if (~crc_error)
136 begin
137 memory[dst[3:0]] <= src;
138
139 case (dst)
140 16'h0000:
141 begin
142 state <= 4'd0;
143 end
144
145 16'h0001:
146 begin
147 int_type <= src[4];
148 int_chan <= src[1:0];
149 int_reset <= 1'b1;
150 state <= 4'd0;
151 end
152
153 16'h0002:
154 begin
155 int_type <= src[4];
156 int_chan <= src[1:0];
157 state <= 4'd3;
158 end
159
160 16'h0003:
161 begin
162 tst_counter <= 11'd0;
163 state <= 4'd6;
164 end
165 16'h0004:
166 begin
167 int_ram_we <= 1'b1;
168 int_ram_data <= 18'd0;
169 ram_counter <= 19'd0;
170 state <= 4'd9;
171 end
172 endcase
173 end
174 end
175
176 // mux transfer
177 3:
178 begin
179 crc_reset <= 1'b0;
180 int_addr <= mux_min_addr;
181 int_max_addr <= mux_min_addr + mux_max_addr;
182 int_max_byte <= mux_max_byte;
183 int_byte <= 2'd0;
184 state <= 4'd4;
185 end
186
187 4:
188 begin
189 int_wrreq <= 1'b0;
190 state <= 4'd5;
191 end
192
193 5:
194 begin
195 if (~tx_full)
196 begin
197 int_data <= mux_q;
198 int_wrreq <= 1'b1;
199 if ((int_byte == int_max_byte) && (int_addr == int_max_addr))
200 begin
201 state <= 4'd0;
202 end
203 else
204 begin
205 state <= 4'd4;
206 if (int_byte == int_max_byte)
207 begin
208 int_addr <= int_addr + 16'd1;
209 int_byte <= 2'd0;
210 end
211 else
212 begin
213 int_byte <= int_byte + 2'd1;
214 end
215 end
216 end
217 end
218
219 // tst transfer
220 6:
221 begin
222 crc_reset <= 1'b0;
223 int_data <= tst_counter;
224 int_wrreq <= 1'b1;
225 tst_counter <= tst_counter + 11'd1;
226 state <= 4'd7;
227 end
228 7:
229 begin
230 if (~tx_full)
231 begin
232 int_data <= tst_counter;
233 if (&tst_counter)
234 begin
235 state <= 4'd8;
236 end
237 else
238 begin
239 tst_counter <= tst_counter + 11'd1;
240 end
241 end
242 end
243 8:
244 begin
245 if (~tx_full)
246 begin
247 int_wrreq <= 1'b0;
248 state <= 4'd0;
249 end
250 end
251 // ram transfer
252 9:
253 begin
254 crc_reset <= 1'b0;
255 state <= 4'd10;
256 end
257 10:
258 begin
259 int_ram_data[8:1] <= ram_counter[7:0];
260// int_ram_data[8:1] <= 8'd0;
261 if (&ram_counter)
262 begin
263 state <= 4'd11;
264 end
265 else
266 begin
267 state <= 4'd9;
268 ram_counter <= ram_counter + 19'd1;
269 end
270 end
271 11:
272 begin
273 int_ram_we <= 1'b0;
274 int_ram_data <= 18'd0;
275 ram_counter <= 19'd0;
276 state <= 4'd12;
277 end
278 12:
279 begin
280 int_wrreq <= 1'b0;
281 state <= 4'd13;
282 end
283 13:
284 begin
285 state <= 4'd14;
286 end
287 14:
288 begin
289 if (~tx_full)
290 begin
291 int_data <= int_ram_q[8:1];
292 int_wrreq <= 1'b1;
293 if (&ram_counter)
294 begin
295 state <= 4'd0;
296 end
297 else
298 begin
299 state <= 4'd12;
300 ram_counter <= ram_counter + 19'd1;
301 end
302 end
303 end
304
305 default:
306 begin
307 state <= 4'd0;
308 end
309 endcase
310 end
311
312 assign mux_reset = int_reset;
313 assign mux_type = int_type;
314 assign mux_chan = int_chan;
315 assign mux_byte = int_byte;
316 assign mux_addr = int_addr;
317 assign rx_rdreq = int_rdreq & (~rx_empty);
318 assign tx_wrreq = int_wrreq & (~tx_full);
319 assign tx_data = int_data;
320 assign led = int_led;
321
322endmodule
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