source: trunk/MultiChannelUSB/control.v@ 72

Last change on this file since 72 was 72, checked in by demin, 15 years ago

testing all components together
File size: 7.0 KB
Line 
1module control
2 (
3 input wire clk,
4
5 output wire cfg_reset,
6 input wire [15:0] cfg_src_data,
7 output wire [15:0] cfg_src_addr, cfg_dst_data, cfg_dst_addr,
8
9 input wire rx_empty, tx_full,
10 input wire [7:0] rx_data,
11
12 input wire [1:0] mux_max_byte,
13 input wire [15:0] mux_min_addr, mux_max_addr,
14 input wire [7:0] mux_q,
15
16 output wire mux_reset,
17 output wire mux_type,
18 output wire [1:0] mux_chan,
19 output wire [1:0] mux_byte,
20 output wire [15:0] mux_addr,
21
22 output wire rx_rdreq,
23 output wire tx_wrreq,
24 output wire [7:0] tx_data,
25
26 output wire ram_we,
27 output wire [19:0] ram_addr,
28 inout wire [17:0] ram_data,
29
30 output wire i2c_wrreq,
31 output wire [15:0] i2c_data,
32 input wire i2c_full,
33
34 output wire led
35 );
36
37 reg [23:0] led_counter;
38 reg [18:0] ram_counter;
39 reg [10:0] tst_counter;
40 reg [15:0] int_addr, int_max_addr;
41
42 reg int_rdreq, int_wrreq;
43 reg int_type, int_reset;
44 reg [1:0] int_chan, int_byte, int_max_byte;
45 reg [7:0] int_data;
46 reg int_led;
47
48 reg [15:0] int_i2c_data;
49 reg int_i2c_wrreq;
50
51 reg int_cfg_reset;
52 reg [15:0] int_dst_data, int_dst_addr;
53
54 wire crc_error = 1'b0;
55 reg crc_reset;
56 reg [2:0] byte_counter;
57 reg [4:0] idle_counter;
58
59 reg [4:0] state;
60
61 wire [15:0] src, dst;
62
63 reg [7:0] buffer [7:0];
64
65 assign src = (buffer[0][7]) ? cfg_src_data : {buffer[2], buffer[3]};
66 assign dst = {1'b0, buffer[0][6:0], buffer[1]};
67
68 reg int_ram_we;
69 reg [17:0] int_ram_data;
70 wire [17:0] int_ram_q;
71 wire [17:0] opt_ram_we;
72 assign ram_we = ~int_ram_we;
73 assign int_ram_q = ram_data;
74// assign ram_data = int_ram_we ? int_ram_data : 18'bz;
75// assign ram_addr = {ram_counter[18:5],1'd0,ram_counter[4:0]};
76 assign ram_addr = {1'd0, ram_counter[18:0]};
77
78 genvar j;
79 generate
80 for (j = 0; j < 18; j = j + 1)
81 begin : SRAM_WE
82 assign opt_ram_we[j] = int_ram_we;
83 assign ram_data[j] = opt_ram_we[j] ? int_ram_data[j] : 1'bz;
84 end
85 endgenerate
86
87 always @(posedge clk)
88 begin
89 if (~rx_empty)
90 begin
91 int_led <= 1'b0;
92 led_counter <= 24'd0;
93 end
94 else
95 begin
96 if (&led_counter)
97 begin
98 int_led <= 1'b1;
99 end
100 else
101 begin
102 led_counter <= led_counter + 24'd1;
103 end
104 end
105
106 case(state)
107 0:
108 begin
109 int_rdreq <= 1'b1;
110 int_wrreq <= 1'b0;
111 int_type <= 1'b0;
112 int_chan <= 2'd0;
113 int_byte <= 2'd0;
114 int_reset <= 1'b0;
115 crc_reset <= 1'b0;
116 int_ram_we <= 1'b0;
117 int_ram_data <= 16'd0;
118 ram_counter <= 19'd0;
119 idle_counter <= 5'd0;
120 byte_counter <= 3'd0;
121 int_cfg_reset <= 1'b0;
122 state <= 5'd1;
123 end
124
125 1:
126 begin
127 // read 8 bytes
128 if (~rx_empty)
129 begin
130 idle_counter <= 5'd0;
131 byte_counter <= byte_counter + 3'd1;
132 buffer[byte_counter] <= rx_data;
133 if (&byte_counter)
134 begin
135 int_rdreq <= 1'b0;
136 state <= 5'd2;
137 end
138 end
139 else if(|byte_counter)
140 begin
141 idle_counter <= idle_counter + 5'd1;
142 if (&idle_counter)
143 begin
144 int_rdreq <= 1'b0;
145 crc_reset <= 1'b1;
146 state <= 5'd0;
147 end
148 end
149 end
150
151 2:
152 begin
153 crc_reset <= 1'b1;
154 if (~crc_error)
155 begin
156 int_dst_addr <= dst;
157 int_dst_data <= src;
158// memory[dst[3:0]] <= src;
159
160 case (dst)
161 16'h0000:
162 begin
163 int_cfg_reset <= 1'b1;
164 state <= 5'd0;
165 end
166
167 16'h0001:
168 begin
169 int_type <= src[4];
170 int_chan <= src[1:0];
171 int_reset <= 1'b1;
172 state <= 5'd0;
173 end
174
175 16'h0002:
176 begin
177 int_type <= src[4];
178 int_chan <= src[1:0];
179 state <= 5'd3;
180 end
181
182 16'h0003:
183 begin
184 tst_counter <= 11'd0;
185 state <= 5'd6;
186 end
187 16'h0004:
188 begin
189 int_ram_we <= 1'b1;
190 int_ram_data <= 18'd0;
191 ram_counter <= 19'd0;
192 state <= 5'd9;
193 end
194 16'h0005:
195 begin
196 int_i2c_data <= src;
197 int_i2c_wrreq <= 1'b1;
198 state <= 5'd15;
199 end
200
201 default:
202 begin
203 state <= 5'd0;
204 end
205 endcase
206 end
207 end
208
209 // mux transfer
210 3:
211 begin
212 crc_reset <= 1'b0;
213 int_addr <= mux_min_addr;
214 int_max_addr <= mux_min_addr + mux_max_addr;
215 int_max_byte <= mux_max_byte;
216 int_byte <= 2'd0;
217 state <= 5'd4;
218 end
219
220 4:
221 begin
222 int_wrreq <= 1'b0;
223 state <= 5'd5;
224 end
225
226 5:
227 begin
228 if (~tx_full)
229 begin
230 int_data <= mux_q;
231 int_wrreq <= 1'b1;
232 if ((int_byte == int_max_byte) && (int_addr == int_max_addr))
233 begin
234 state <= 5'd0;
235 end
236 else
237 begin
238 state <= 5'd4;
239 if (int_byte == int_max_byte)
240 begin
241 int_addr <= int_addr + 16'd1;
242 int_byte <= 2'd0;
243 end
244 else
245 begin
246 int_byte <= int_byte + 2'd1;
247 end
248 end
249 end
250 end
251
252 // tst transfer
253 6:
254 begin
255 crc_reset <= 1'b0;
256 int_data <= tst_counter;
257 int_wrreq <= 1'b1;
258 tst_counter <= tst_counter + 11'd1;
259 state <= 5'd7;
260 end
261 7:
262 begin
263 if (~tx_full)
264 begin
265 int_data <= tst_counter;
266 if (&tst_counter)
267 begin
268 state <= 5'd8;
269 end
270 else
271 begin
272 tst_counter <= tst_counter + 11'd1;
273 end
274 end
275 end
276 8:
277 begin
278 if (~tx_full)
279 begin
280 int_wrreq <= 1'b0;
281 state <= 5'd0;
282 end
283 end
284 // ram transfer
285 9:
286 begin
287 crc_reset <= 1'b0;
288 state <= 5'd10;
289 end
290 10:
291 begin
292 int_ram_data[8:1] <= ram_counter[7:0];
293// int_ram_data[8:1] <= 8'd0;
294 if (&ram_counter)
295 begin
296 state <= 5'd11;
297 end
298 else
299 begin
300 state <= 5'd9;
301 ram_counter <= ram_counter + 19'd1;
302 end
303 end
304 11:
305 begin
306 int_ram_we <= 1'b0;
307 int_ram_data <= 18'd0;
308 ram_counter <= 19'd0;
309 state <= 5'd12;
310 end
311 12:
312 begin
313 int_wrreq <= 1'b0;
314 state <= 5'd13;
315 end
316 13:
317 begin
318 state <= 5'd14;
319 end
320 14:
321 begin
322 if (~tx_full)
323 begin
324 int_data <= int_ram_q[8:1];
325 int_wrreq <= 1'b1;
326 if (&ram_counter)
327 begin
328 state <= 5'd0;
329 end
330 else
331 begin
332 state <= 5'd12;
333 ram_counter <= ram_counter + 19'd1;
334 end
335 end
336 end
337
338 // i2c write
339 15:
340 begin
341 crc_reset <= 1'b0;
342 if (~i2c_full)
343 begin
344 int_i2c_wrreq <= 1'b0;
345 state <= 5'd0;
346 end
347 end
348
349 default:
350 begin
351 state <= 5'd0;
352 end
353 endcase
354 end
355
356 assign cfg_reset = int_cfg_reset;
357 assign cfg_src_addr = {buffer[2], buffer[3]};
358 assign cfg_dst_data = int_dst_data;
359 assign cfg_dst_addr = int_dst_addr;
360 assign mux_reset = int_reset;
361 assign mux_type = int_type;
362 assign mux_chan = int_chan;
363 assign mux_byte = int_byte;
364 assign mux_addr = int_addr;
365 assign rx_rdreq = int_rdreq & (~rx_empty);
366 assign tx_wrreq = int_wrreq & (~tx_full);
367 assign tx_data = int_data;
368 assign i2c_wrreq = int_i2c_wrreq;
369 assign i2c_data = int_i2c_data;
370 assign led = int_led;
371
372endmodule
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