Last change
on this file since 108 was 99, checked in by demin, 14 years ago |
double the number of configuration registers
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File size:
1.5 KB
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1 | module configuration
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2 | (
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3 | input wire clock, reset,
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4 |
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5 | input wire bus_ssel, bus_wren,
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6 | input wire [4:0] bus_addr,
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7 | input wire [15:0] bus_mosi,
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8 |
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9 | output wire [15:0] bus_miso,
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10 | output wire bus_busy,
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11 |
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12 | output wire [511:0] cfg_bits
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13 | );
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14 |
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15 | wire [31:0] int_ssel_wire;
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16 | wire [15:0] int_miso_wire;
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17 | reg [15:0] int_miso_reg;
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18 |
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19 | wire [511:0] int_bits_wire;
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20 |
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21 | integer i;
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22 | genvar j;
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23 |
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24 | generate
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25 | for (j = 0; j < 32; j = j + 1)
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26 | begin : BUS_OUTPUT
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27 | lpm_ff #(
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28 | .lpm_fftype("DFF"),
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29 | .lpm_type("LPM_FF"),
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30 | .lpm_width(16)) cfg_reg_unit (
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31 | .enable(int_ssel_wire[j] & bus_ssel & bus_wren),
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32 | .sclr(reset),
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33 | .clock(clock),
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34 | .data(bus_mosi),
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35 | .q(int_bits_wire[j*16+15:j*16]),
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36 | .aclr(),
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37 | .aload(),
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38 | .aset(),
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39 | .sload(),
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40 | .sset());
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41 | end
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42 | endgenerate
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43 |
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44 | lpm_mux #(
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45 | .lpm_size(32),
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46 | .lpm_type("LPM_MUX"),
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47 | .lpm_width(16),
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48 | .lpm_widths(5)) bus_miso_mux_unit (
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49 | .sel(bus_addr),
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50 | .data(int_bits_wire),
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51 | .result(int_miso_wire));
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52 |
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53 |
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54 | lpm_decode #(
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55 | .lpm_decodes(32),
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56 | .lpm_type("LPM_DECODE"),
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57 | .lpm_width(5)) lpm_decode_unit (
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58 | .data(bus_addr),
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59 | .eq(int_ssel_wire),
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60 | .aclr(),
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61 | .clken(),
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62 | .clock(),
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63 | .enable());
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64 |
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65 | always @(posedge clock)
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66 | begin
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67 | if (reset)
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68 | begin
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69 | int_miso_reg <= 16'd0;
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70 | end
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71 | else
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72 | begin
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73 | int_miso_reg <= int_miso_wire;
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74 | end
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75 | end
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76 |
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77 | // output logic
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78 | assign bus_miso = int_miso_reg;
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79 | assign bus_busy = 1'b0;
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80 | assign cfg_bits = int_bits_wire;
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81 |
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82 | endmodule
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