Rev | Line | |
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[90] | 1 | module configuration
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| 2 | (
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| 3 | input wire clock, reset,
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| 4 |
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| 5 | input wire bus_ssel, bus_wren,
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| 6 | input wire [3:0] bus_addr,
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| 7 | input wire [15:0] bus_mosi,
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| 8 |
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| 9 | output wire [15:0] bus_miso,
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| 10 | output wire bus_busy,
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| 11 |
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| 12 | output wire [255:0] cfg_bits
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| 13 | );
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| 14 |
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| 15 | wire [15:0] int_ssel_wire;
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| 16 | wire [15:0] int_miso_wire;
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| 17 | reg [15:0] int_miso_reg [3:0];
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| 18 |
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| 19 | wire [15:0] int_q_wire [15:0];
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| 20 | wire [255:0] int_bits_wire;
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| 21 |
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| 22 | integer i;
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| 23 | genvar j;
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| 24 |
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| 25 | generate
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| 26 | for (j = 0; j < 16; j = j + 1)
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| 27 | begin : BUS_OUTPUT
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| 28 | assign int_bits_wire[j*16+15:j*16] = int_q_wire[j];
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| 29 | lpm_ff #(
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| 30 | .lpm_fftype("DFF"),
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| 31 | .lpm_type("LPM_FF"),
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| 32 | .lpm_width(16)) cfg_reg_unit (
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| 33 | .enable(int_ssel_wire[j] & bus_ssel & bus_wren),
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| 34 | .sclr(reset),
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| 35 | .clock(clock),
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| 36 | .data(bus_mosi),
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| 37 | .q(int_q_wire[j]),
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| 38 | .aclr(),
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| 39 | .aload(),
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| 40 | .aset(),
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| 41 | .sload(),
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| 42 | .sset());
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| 43 | end
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| 44 | endgenerate
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| 45 |
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| 46 | lpm_mux #(
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| 47 | .lpm_size(16),
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| 48 | .lpm_type("LPM_MUX"),
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| 49 | .lpm_width(16),
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| 50 | .lpm_widths(4)) bus_miso_mux_unit (
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| 51 | .sel(bus_addr),
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| 52 | .data(int_bits_wire),
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| 53 | .result(int_miso_wire));
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| 54 |
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| 55 |
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| 56 | lpm_decode #(
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| 57 | .lpm_decodes(16),
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| 58 | .lpm_type("LPM_DECODE"),
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| 59 | .lpm_width(4)) lpm_decode_unit (
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| 60 | .data(bus_addr),
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| 61 | .eq(int_ssel_wire),
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| 62 | .aclr(),
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| 63 | .clken(),
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| 64 | .clock(),
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| 65 | .enable());
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| 66 |
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| 67 | always @(posedge clock)
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| 68 | begin
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| 69 | if (reset)
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| 70 | begin
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| 71 | for(i = 0; i <= 3; i = i + 1)
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| 72 | begin
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| 73 | int_miso_reg[i] <= 16'd0;
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| 74 | end
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| 75 | end
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| 76 | else
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| 77 | begin
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| 78 | for(i = 0; i < 3; i = i + 1)
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| 79 | begin
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| 80 | int_miso_reg[i+1] <= int_miso_reg[i];
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| 81 | end
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| 82 | int_miso_reg[0] <= int_miso_wire;
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| 83 | end
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| 84 | end
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| 85 |
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| 86 | // output logic
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| 87 | assign bus_miso = int_miso_reg[3];
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| 88 | assign bus_busy = 1'b0;
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| 89 | assign cfg_bits = int_bits_wire;
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| 90 |
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| 91 | endmodule
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