| 1 | module clip
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| 2 | #(
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| 3 | parameter shift = 24, // right shift of the result
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| 4 | parameter width = 27, // bit width of the input data
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| 5 | parameter widthr = 12 // bit width of the output data
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| 6 | )
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| 7 | (
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| 8 | input wire clock, frame, reset,
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| 9 | input wire [4*6-1:0] del_data,
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| 10 | input wire [4*6-1:0] amp_data,
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| 11 | input wire [4*16-1:0] tau_data,
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| 12 | input wire [4*width-1:0] inp_data,
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| 13 | output wire [4*widthr-1:0] out_data
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| 14 | );
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| 15 |
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| 16 | localparam width1 = width + 16;
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| 17 | localparam width2 = width + 6;
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| 18 | localparam width3 = width1 + 2;
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| 19 |
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| 20 | reg int_wren_reg, int_wren_next;
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| 21 | reg int_flag_reg, int_flag_next;
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| 22 | reg [1:0] int_chan_reg, int_chan_next;
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| 23 | reg [2:0] int_case_reg, int_case_next;
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| 24 | reg [7:0] int_addr_reg, int_addr_next;
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| 25 |
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| 26 | reg [5:0] del_addr_reg, del_addr_next;
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| 27 | wire [5:0] del_addr_wire;
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| 28 | wire [7:0] int_addr_wire;
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| 29 |
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| 30 | reg [widthr-1:0] out_data_reg [4:0], out_data_next [4:0];
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| 31 | wire [widthr-1:0] out_data_wire;
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| 32 |
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| 33 | reg [width3-1:0] add_data_reg [4:0], add_data_next [4:0];
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| 34 | wire [width3-1:0] add_data_wire;
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| 35 |
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| 36 | wire [width1-1:0] mul_data_wire1;
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| 37 | wire [width2-1:0] mul_data_wire2;
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| 38 |
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| 39 | reg [width-1:0] inp_data_reg [3:0], inp_data_next [3:0];
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| 40 | wire [width-1:0] inp_data_wire [4:0];
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| 41 |
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| 42 | reg [5:0] amp_data_reg, amp_data_next;
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| 43 | wire [5:0] amp_data_wire [3:0];
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| 44 |
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| 45 | reg [15:0] tau_data_reg, tau_data_next;
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| 46 | wire [15:0] tau_data_wire [3:0];
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| 47 |
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| 48 | integer i;
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| 49 | genvar j;
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| 50 |
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| 51 | generate
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| 52 | for (j = 0; j < 4; j = j + 1)
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| 53 | begin : INT_DATA
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| 54 | assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
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| 55 | assign amp_data_wire[j] = amp_data[j*6+6-1:j*6];
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| 56 | assign tau_data_wire[j] = tau_data[j*16+16-1:j*16];
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| 57 | end
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| 58 | endgenerate
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| 59 |
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| 60 | lpm_mux #(
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| 61 | .lpm_size(4),
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| 62 | .lpm_type("LPM_MUX"),
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| 63 | .lpm_width(8),
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| 64 | .lpm_widths(2)) mux_unit_1 (
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| 65 | .sel(int_chan_next),
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| 66 | .data({
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| 67 | 2'd3, del_data[3*6+6-1:3*6],
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| 68 | 2'd2, del_data[2*6+6-1:2*6],
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| 69 | 2'd1, del_data[1*6+6-1:1*6],
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| 70 | 2'd0, del_data[0*6+6-1:0*6]}),
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| 71 | .result(int_addr_wire));
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| 72 |
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| 73 | assign del_addr_wire = del_addr_reg - int_addr_wire[5:0];
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| 74 |
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| 75 | lpm_mult #(
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| 76 | .lpm_hint("MAXIMIZE_SPEED=9"),
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| 77 | .lpm_representation("UNSIGNED"),
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| 78 | .lpm_type("LPM_MULT"),
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| 79 | .lpm_pipeline(3),
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| 80 | .lpm_widtha(width),
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| 81 | .lpm_widthb(16),
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| 82 | .lpm_widthp(width1)) mult_unit_1 (
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| 83 | .clock(clock),
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| 84 | .clken(int_wren_reg),
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| 85 | .dataa(inp_data_wire[4]),
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| 86 | .datab(tau_data_reg),
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| 87 | .result(mul_data_wire1));
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| 88 |
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| 89 | lpm_mult #(
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| 90 | .lpm_hint("MAXIMIZE_SPEED=9"),
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| 91 | .lpm_representation("UNSIGNED"),
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| 92 | .lpm_type("LPM_MULT"),
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| 93 | .lpm_pipeline(3),
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| 94 | .lpm_widtha(width),
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| 95 | .lpm_widthb(6),
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| 96 | .lpm_widthp(width2)) mult_unit_2 (
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| 97 | .clock(clock),
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| 98 | .clken(int_wren_reg),
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| 99 | .dataa(inp_data_reg[0]),
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| 100 | .datab(amp_data_reg),
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| 101 | .result(mul_data_wire2));
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| 102 |
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| 103 | assign add_data_wire =
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| 104 | {2'b0, mul_data_wire2, {(width1-width2){1'b0}}}
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| 105 | - {2'b0, mul_data_wire1};
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| 106 |
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| 107 | assign out_data_wire = add_data_reg[0][width3-1] ? {(widthr){1'b0}} :
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| 108 | add_data_reg[0][shift+widthr-1:shift]
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| 109 | + {{(widthr-1){add_data_reg[0][width3-1]}}, add_data_reg[0][shift-1]};
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| 110 |
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| 111 |
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| 112 | altsyncram #(
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| 113 | .address_aclr_b("NONE"),
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| 114 | .address_reg_b("CLOCK0"),
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| 115 | .clock_enable_input_a("BYPASS"),
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| 116 | .clock_enable_input_b("BYPASS"),
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| 117 | .clock_enable_output_b("BYPASS"),
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| 118 | .intended_device_family("Cyclone III"),
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| 119 | .lpm_type("altsyncram"),
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| 120 | .numwords_a(256),
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| 121 | .numwords_b(256),
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| 122 | .operation_mode("DUAL_PORT"),
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| 123 | .outdata_aclr_b("NONE"),
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| 124 | .outdata_reg_b("CLOCK0"),
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| 125 | .power_up_uninitialized("FALSE"),
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| 126 | .read_during_write_mode_mixed_ports("DONT_CARE"),
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| 127 | .widthad_a(8),
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| 128 | .widthad_b(8),
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| 129 | .width_a(width),
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| 130 | .width_b(width),
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| 131 | .width_byteena_a(1)) ram_unit_1 (
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| 132 | .wren_a(int_wren_reg),
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| 133 | .clock0(clock),
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| 134 | .address_a(int_addr_reg),
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| 135 | .address_b({int_addr_wire[7:6], del_addr_wire}),
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| 136 | .data_a(inp_data_reg[0]),
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| 137 | .q_b(inp_data_wire[4]),
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| 138 | .aclr0(1'b0),
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| 139 | .aclr1(1'b0),
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| 140 | .addressstall_a(1'b0),
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| 141 | .addressstall_b(1'b0),
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| 142 | .byteena_a(1'b1),
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| 143 | .byteena_b(1'b1),
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| 144 | .clock1(1'b1),
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| 145 | .clocken0(1'b1),
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| 146 | .clocken1(1'b1),
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| 147 | .clocken2(1'b1),
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| 148 | .clocken3(1'b1),
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| 149 | .data_b({(width){1'b1}}),
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| 150 | .eccstatus(),
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| 151 | .q_a(),
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| 152 | .rden_a(1'b1),
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| 153 | .rden_b(1'b1),
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| 154 | .wren_b(1'b0));
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| 155 |
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| 156 | always @(posedge clock)
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| 157 | begin
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| 158 | if (reset)
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| 159 | begin
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| 160 | int_wren_reg <= 1'b1;
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| 161 | int_flag_reg <= 1'b0;
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| 162 | int_chan_reg <= 2'd0;
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| 163 | int_case_reg <= 3'd0;
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| 164 | del_addr_reg <= 6'd0;
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| 165 | int_addr_reg <= 8'd0;
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| 166 | amp_data_reg <= 6'd0;
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| 167 | tau_data_reg <= 16'd0;
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| 168 | for(i = 0; i <= 3; i = i + 1)
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| 169 | begin
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| 170 | inp_data_reg[i] <= {(width){1'b0}};
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| 171 | end
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| 172 | for(i = 0; i <= 4; i = i + 1)
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| 173 | begin
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| 174 | out_data_reg[i] <= {(widthr){1'b0}};
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| 175 | add_data_reg[i] <= {(width3){1'b0}};
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| 176 | end
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| 177 | end
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| 178 | else
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| 179 | begin
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| 180 | int_wren_reg <= int_wren_next;
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| 181 | int_flag_reg <= int_flag_next;
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| 182 | int_chan_reg <= int_chan_next;
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| 183 | int_case_reg <= int_case_next;
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| 184 | del_addr_reg <= del_addr_next;
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| 185 | int_addr_reg <= int_addr_next;
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| 186 | amp_data_reg <= amp_data_next;
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| 187 | tau_data_reg <= tau_data_next;
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| 188 | for(i = 0; i <= 3; i = i + 1)
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| 189 | begin
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| 190 | inp_data_reg[i] <= inp_data_next[i];
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| 191 | end
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| 192 | for(i = 0; i <= 4; i = i + 1)
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| 193 | begin
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| 194 | out_data_reg[i] <= out_data_next[i];
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| 195 | add_data_reg[i] <= add_data_next[i];
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| 196 | end
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| 197 | end
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| 198 | end
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| 199 |
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| 200 | always @*
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| 201 | begin
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| 202 | int_wren_next = int_wren_reg;
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| 203 | int_flag_next = int_flag_reg;
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| 204 | int_chan_next = int_chan_reg;
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| 205 | int_case_next = int_case_reg;
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| 206 | del_addr_next = del_addr_reg;
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| 207 | int_addr_next = int_addr_reg;
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| 208 | amp_data_next = amp_data_reg;
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| 209 | tau_data_next = tau_data_reg;
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| 210 | for(i = 0; i <= 3; i = i + 1)
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| 211 | begin
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| 212 | inp_data_next[i] = inp_data_reg[i];
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| 213 | end
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| 214 | for(i = 0; i <= 4; i = i + 1)
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| 215 | begin
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| 216 | out_data_next[i] = out_data_reg[i];
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| 217 | add_data_next[i] = add_data_reg[i];
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| 218 | end
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| 219 |
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| 220 | case (int_case_reg)
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| 221 | 0:
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| 222 | begin
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| 223 | // write zeros
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| 224 | int_wren_next = 1'b1;
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| 225 | del_addr_next = 6'd0;
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| 226 | int_addr_next = 8'd0;
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| 227 | amp_data_next = 6'd0;
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| 228 | tau_data_next = 16'd0;
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| 229 | for(i = 0; i <= 3; i = i + 1)
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| 230 | begin
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| 231 | inp_data_next[i] = {(width){1'b0}};
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| 232 | end
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| 233 | for(i = 0; i <= 4; i = i + 1)
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| 234 | begin
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| 235 | out_data_next[i] = {(widthr){1'b0}};
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| 236 | add_data_next[i] = {(width3){1'b0}};
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| 237 | end
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| 238 |
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| 239 | int_case_next = 3'd1;
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| 240 | end
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| 241 | 1:
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| 242 | begin
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| 243 | // write zeros
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| 244 | int_addr_next = int_addr_reg + 8'd1;
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| 245 | if (&int_addr_reg)
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| 246 | begin
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| 247 | int_wren_next = 1'b0;
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| 248 | int_flag_next = 1'b0;
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| 249 | int_chan_next = 2'd0;
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| 250 | int_case_next = 3'd2;
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| 251 | end
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| 252 | end
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| 253 | 2: // frame
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| 254 | begin
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| 255 | int_flag_next = 1'b0;
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| 256 | int_wren_next = frame;
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| 257 | if (frame)
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| 258 | begin
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| 259 | int_addr_next[7:6] = 2'd0;
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| 260 |
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| 261 | // set read addr for 2nd pipeline
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| 262 | int_chan_next = 2'd1;
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| 263 |
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| 264 | // register input data for 2nd, 3rd and 4th sums
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| 265 | inp_data_next[1] = inp_data_wire[1];
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| 266 | inp_data_next[2] = inp_data_wire[2];
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| 267 | inp_data_next[3] = inp_data_wire[3];
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| 268 |
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| 269 | // prepare registers for 1st sum
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| 270 | inp_data_next[0] = inp_data_wire[0];
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| 271 | // prepare registers for 2nd shift
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| 272 | add_data_next[0] = add_data_reg[2];
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| 273 |
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| 274 | tau_data_next = tau_data_wire[0];
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| 275 | amp_data_next = amp_data_wire[0];
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| 276 |
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| 277 | int_case_next = 3'd3;
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| 278 | end
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| 279 | if (int_flag_reg) // register 4th sum
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| 280 | begin
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| 281 | int_addr_next[5:0] = del_addr_reg;
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| 282 | // register 1st product
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| 283 | add_data_next[1] = add_data_wire;
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| 284 | out_data_next[1] = out_data_wire;
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| 285 | end
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| 286 | end
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| 287 | 3: // 1st sum
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| 288 | begin
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| 289 | int_addr_next[7:6] = 2'd1;
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| 290 |
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| 291 | // set read addr for 3rd pipeline
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| 292 | int_chan_next = 2'd2;
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| 293 |
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| 294 | // prepare registers for 2nd sum
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| 295 | inp_data_next[0] = inp_data_reg[1];
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| 296 | // prepare registers for 3rd shift
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| 297 | add_data_next[0] = add_data_reg[3];
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| 298 |
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| 299 | tau_data_next = tau_data_wire[1];
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| 300 | amp_data_next = amp_data_wire[1];
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| 301 |
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| 302 | // register 2nd product
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| 303 | add_data_next[2] = add_data_wire;
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| 304 | out_data_next[2] = out_data_wire;
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| 305 |
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| 306 | int_case_next = 3'd4;
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| 307 | end
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| 308 | 4: // 2nd sum
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| 309 | begin
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| 310 | int_addr_next[7:6] = 2'd2;
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| 311 |
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| 312 | // set read addr for 4th pipeline
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| 313 | int_chan_next = 2'd3;
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| 314 |
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| 315 | // prepare registers for 3rd sum
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| 316 | inp_data_next[0] = inp_data_reg[2];
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| 317 | // prepare registers for 4th shift
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| 318 | add_data_next[0] = add_data_reg[4];
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| 319 |
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| 320 | tau_data_next = tau_data_wire[2];
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| 321 | amp_data_next = amp_data_wire[2];
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| 322 |
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| 323 | // register 3rd product
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| 324 | add_data_next[3] = add_data_wire;
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| 325 | out_data_next[3] = out_data_wire;
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| 326 |
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| 327 | del_addr_next = del_addr_reg + 6'd1;
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| 328 |
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| 329 | int_case_next = 3'd5;
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| 330 | end
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| 331 | 5: // 3rd sum
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| 332 | begin
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| 333 | int_flag_next = 1'b1;
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| 334 |
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| 335 | int_addr_next[7:6] = 2'd3;
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| 336 |
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| 337 | // set read addr for 1st pipeline
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| 338 | int_chan_next = 2'd0;
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| 339 |
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| 340 | // prepare registers for 4th sum
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| 341 | inp_data_next[0] = inp_data_reg[3];
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| 342 | // prepare registers for 1st shift
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| 343 | add_data_next[0] = add_data_reg[1];
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| 344 |
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| 345 | tau_data_next = tau_data_wire[3];
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| 346 | amp_data_next = amp_data_wire[3];
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| 347 |
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| 348 | // register 4th product
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| 349 | add_data_next[4] = add_data_wire;
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| 350 | out_data_next[4] = out_data_wire;
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| 351 |
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| 352 | // register 4th output
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| 353 | out_data_next[0] = out_data_reg[1];
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| 354 |
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| 355 | int_case_next = 3'd2;
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| 356 | end
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| 357 | default:
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| 358 | begin
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| 359 | int_case_next = 3'd0;
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| 360 | end
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| 361 | endcase
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| 362 | end
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| 363 |
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| 364 | assign out_data = {out_data_reg[4], out_data_reg[3], out_data_reg[2], out_data_reg[0]};
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| 365 |
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| 366 | endmodule
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