source: trunk/MultiChannelUSB/clip.v@ 187

Last change on this file since 187 was 159, checked in by demin, 13 years ago

adapt to paella v2
File size: 9.2 KB
RevLine 
[159]1module clip
2 #(
3 parameter shift = 24, // right shift of the result
4 parameter width = 27, // bit width of the input data
5 parameter widthr = 12 // bit width of the output data
6 )
7 (
8 input wire clock, frame, reset,
9 input wire [4*6-1:0] del_data,
10 input wire [4*6-1:0] amp_data,
11 input wire [4*16-1:0] tau_data,
12 input wire [4*width-1:0] inp_data,
13 output wire [4*widthr-1:0] out_data
14 );
15
16 localparam width1 = width + 16;
17 localparam width2 = width + 6;
18 localparam width3 = width1 + 2;
19
20 reg int_wren_reg, int_wren_next;
21 reg int_flag_reg, int_flag_next;
22 reg [1:0] int_chan_reg, int_chan_next;
23 reg [2:0] int_case_reg, int_case_next;
24 reg [7:0] int_addr_reg, int_addr_next;
25
26 reg [5:0] del_addr_reg, del_addr_next;
27 wire [5:0] del_addr_wire;
28 wire [7:0] int_addr_wire;
29
30 reg [widthr-1:0] out_data_reg [4:0], out_data_next [4:0];
31 wire [widthr-1:0] out_data_wire;
32
33 reg [width3-1:0] add_data_reg [4:0], add_data_next [4:0];
34 wire [width3-1:0] add_data_wire;
35
36 wire [width1-1:0] mul_data_wire1;
37 wire [width2-1:0] mul_data_wire2;
38
39 reg [width-1:0] inp_data_reg [3:0], inp_data_next [3:0];
40 wire [width-1:0] inp_data_wire [4:0];
41
42 reg [5:0] amp_data_reg, amp_data_next;
43 wire [5:0] amp_data_wire [3:0];
44
45 reg [15:0] tau_data_reg, tau_data_next;
46 wire [15:0] tau_data_wire [3:0];
47
48 integer i;
49 genvar j;
50
51 generate
52 for (j = 0; j < 4; j = j + 1)
53 begin : INT_DATA
54 assign inp_data_wire[j] = inp_data[j*width+width-1:j*width];
55 assign amp_data_wire[j] = amp_data[j*6+6-1:j*6];
56 assign tau_data_wire[j] = tau_data[j*16+16-1:j*16];
57 end
58 endgenerate
59
60 lpm_mux #(
61 .lpm_size(4),
62 .lpm_type("LPM_MUX"),
63 .lpm_width(8),
64 .lpm_widths(2)) mux_unit_1 (
65 .sel(int_chan_next),
66 .data({
67 2'd3, del_data[3*6+6-1:3*6],
68 2'd2, del_data[2*6+6-1:2*6],
69 2'd1, del_data[1*6+6-1:1*6],
70 2'd0, del_data[0*6+6-1:0*6]}),
71 .result(int_addr_wire));
72
73 assign del_addr_wire = del_addr_reg - int_addr_wire[5:0];
74
75 lpm_mult #(
76 .lpm_hint("MAXIMIZE_SPEED=9"),
77 .lpm_representation("UNSIGNED"),
78 .lpm_type("LPM_MULT"),
79 .lpm_pipeline(3),
80 .lpm_widtha(width),
81 .lpm_widthb(16),
82 .lpm_widthp(width1)) mult_unit_1 (
83 .clock(clock),
84 .clken(int_wren_reg),
85 .dataa(inp_data_wire[4]),
86 .datab(tau_data_reg),
87 .result(mul_data_wire1));
88
89 lpm_mult #(
90 .lpm_hint("MAXIMIZE_SPEED=9"),
91 .lpm_representation("UNSIGNED"),
92 .lpm_type("LPM_MULT"),
93 .lpm_pipeline(3),
94 .lpm_widtha(width),
95 .lpm_widthb(6),
96 .lpm_widthp(width2)) mult_unit_2 (
97 .clock(clock),
98 .clken(int_wren_reg),
99 .dataa(inp_data_reg[0]),
100 .datab(amp_data_reg),
101 .result(mul_data_wire2));
102
103 assign add_data_wire =
104 {2'b0, mul_data_wire2, {(width1-width2){1'b0}}}
105 - {2'b0, mul_data_wire1};
106
107 assign out_data_wire = add_data_reg[0][width3-1] ? {(widthr){1'b0}} :
108 add_data_reg[0][shift+widthr-1:shift]
109 + {{(widthr-1){add_data_reg[0][width3-1]}}, add_data_reg[0][shift-1]};
110
111
112 altsyncram #(
113 .address_aclr_b("NONE"),
114 .address_reg_b("CLOCK0"),
115 .clock_enable_input_a("BYPASS"),
116 .clock_enable_input_b("BYPASS"),
117 .clock_enable_output_b("BYPASS"),
118 .intended_device_family("Cyclone III"),
119 .lpm_type("altsyncram"),
120 .numwords_a(256),
121 .numwords_b(256),
122 .operation_mode("DUAL_PORT"),
123 .outdata_aclr_b("NONE"),
124 .outdata_reg_b("CLOCK0"),
125 .power_up_uninitialized("FALSE"),
126 .read_during_write_mode_mixed_ports("DONT_CARE"),
127 .widthad_a(8),
128 .widthad_b(8),
129 .width_a(width),
130 .width_b(width),
131 .width_byteena_a(1)) ram_unit_1 (
132 .wren_a(int_wren_reg),
133 .clock0(clock),
134 .address_a(int_addr_reg),
135 .address_b({int_addr_wire[7:6], del_addr_wire}),
136 .data_a(inp_data_reg[0]),
137 .q_b(inp_data_wire[4]),
138 .aclr0(1'b0),
139 .aclr1(1'b0),
140 .addressstall_a(1'b0),
141 .addressstall_b(1'b0),
142 .byteena_a(1'b1),
143 .byteena_b(1'b1),
144 .clock1(1'b1),
145 .clocken0(1'b1),
146 .clocken1(1'b1),
147 .clocken2(1'b1),
148 .clocken3(1'b1),
149 .data_b({(width){1'b1}}),
150 .eccstatus(),
151 .q_a(),
152 .rden_a(1'b1),
153 .rden_b(1'b1),
154 .wren_b(1'b0));
155
156 always @(posedge clock)
157 begin
158 if (reset)
159 begin
160 int_wren_reg <= 1'b1;
161 int_flag_reg <= 1'b0;
162 int_chan_reg <= 2'd0;
163 int_case_reg <= 3'd0;
164 del_addr_reg <= 6'd0;
165 int_addr_reg <= 8'd0;
166 amp_data_reg <= 6'd0;
167 tau_data_reg <= 16'd0;
168 for(i = 0; i <= 3; i = i + 1)
169 begin
170 inp_data_reg[i] <= {(width){1'b0}};
171 end
172 for(i = 0; i <= 4; i = i + 1)
173 begin
174 out_data_reg[i] <= {(widthr){1'b0}};
175 add_data_reg[i] <= {(width3){1'b0}};
176 end
177 end
178 else
179 begin
180 int_wren_reg <= int_wren_next;
181 int_flag_reg <= int_flag_next;
182 int_chan_reg <= int_chan_next;
183 int_case_reg <= int_case_next;
184 del_addr_reg <= del_addr_next;
185 int_addr_reg <= int_addr_next;
186 amp_data_reg <= amp_data_next;
187 tau_data_reg <= tau_data_next;
188 for(i = 0; i <= 3; i = i + 1)
189 begin
190 inp_data_reg[i] <= inp_data_next[i];
191 end
192 for(i = 0; i <= 4; i = i + 1)
193 begin
194 out_data_reg[i] <= out_data_next[i];
195 add_data_reg[i] <= add_data_next[i];
196 end
197 end
198 end
199
200 always @*
201 begin
202 int_wren_next = int_wren_reg;
203 int_flag_next = int_flag_reg;
204 int_chan_next = int_chan_reg;
205 int_case_next = int_case_reg;
206 del_addr_next = del_addr_reg;
207 int_addr_next = int_addr_reg;
208 amp_data_next = amp_data_reg;
209 tau_data_next = tau_data_reg;
210 for(i = 0; i <= 3; i = i + 1)
211 begin
212 inp_data_next[i] = inp_data_reg[i];
213 end
214 for(i = 0; i <= 4; i = i + 1)
215 begin
216 out_data_next[i] = out_data_reg[i];
217 add_data_next[i] = add_data_reg[i];
218 end
219
220 case (int_case_reg)
221 0:
222 begin
223 // write zeros
224 int_wren_next = 1'b1;
225 del_addr_next = 6'd0;
226 int_addr_next = 8'd0;
227 amp_data_next = 6'd0;
228 tau_data_next = 16'd0;
229 for(i = 0; i <= 3; i = i + 1)
230 begin
231 inp_data_next[i] = {(width){1'b0}};
232 end
233 for(i = 0; i <= 4; i = i + 1)
234 begin
235 out_data_next[i] = {(widthr){1'b0}};
236 add_data_next[i] = {(width3){1'b0}};
237 end
238
239 int_case_next = 3'd1;
240 end
241 1:
242 begin
243 // write zeros
244 int_addr_next = int_addr_reg + 8'd1;
245 if (&int_addr_reg)
246 begin
247 int_wren_next = 1'b0;
248 int_flag_next = 1'b0;
249 int_chan_next = 2'd0;
250 int_case_next = 3'd2;
251 end
252 end
253 2: // frame
254 begin
255 int_flag_next = 1'b0;
256 int_wren_next = frame;
257 if (frame)
258 begin
259 int_addr_next[7:6] = 2'd0;
260
261 // set read addr for 2nd pipeline
262 int_chan_next = 2'd1;
263
264 // register input data for 2nd, 3rd and 4th sums
265 inp_data_next[1] = inp_data_wire[1];
266 inp_data_next[2] = inp_data_wire[2];
267 inp_data_next[3] = inp_data_wire[3];
268
269 // prepare registers for 1st sum
270 inp_data_next[0] = inp_data_wire[0];
271 // prepare registers for 2nd shift
272 add_data_next[0] = add_data_reg[2];
273
274 tau_data_next = tau_data_wire[0];
275 amp_data_next = amp_data_wire[0];
276
277 int_case_next = 3'd3;
278 end
279 if (int_flag_reg) // register 4th sum
280 begin
281 int_addr_next[5:0] = del_addr_reg;
282 // register 1st product
283 add_data_next[1] = add_data_wire;
284 out_data_next[1] = out_data_wire;
285 end
286 end
287 3: // 1st sum
288 begin
289 int_addr_next[7:6] = 2'd1;
290
291 // set read addr for 3rd pipeline
292 int_chan_next = 2'd2;
293
294 // prepare registers for 2nd sum
295 inp_data_next[0] = inp_data_reg[1];
296 // prepare registers for 3rd shift
297 add_data_next[0] = add_data_reg[3];
298
299 tau_data_next = tau_data_wire[1];
300 amp_data_next = amp_data_wire[1];
301
302 // register 2nd product
303 add_data_next[2] = add_data_wire;
304 out_data_next[2] = out_data_wire;
305
306 int_case_next = 3'd4;
307 end
308 4: // 2nd sum
309 begin
310 int_addr_next[7:6] = 2'd2;
311
312 // set read addr for 4th pipeline
313 int_chan_next = 2'd3;
314
315 // prepare registers for 3rd sum
316 inp_data_next[0] = inp_data_reg[2];
317 // prepare registers for 4th shift
318 add_data_next[0] = add_data_reg[4];
319
320 tau_data_next = tau_data_wire[2];
321 amp_data_next = amp_data_wire[2];
322
323 // register 3rd product
324 add_data_next[3] = add_data_wire;
325 out_data_next[3] = out_data_wire;
326
327 del_addr_next = del_addr_reg + 6'd1;
328
329 int_case_next = 3'd5;
330 end
331 5: // 3rd sum
332 begin
333 int_flag_next = 1'b1;
334
335 int_addr_next[7:6] = 2'd3;
336
337 // set read addr for 1st pipeline
338 int_chan_next = 2'd0;
339
340 // prepare registers for 4th sum
341 inp_data_next[0] = inp_data_reg[3];
342 // prepare registers for 1st shift
343 add_data_next[0] = add_data_reg[1];
344
345 tau_data_next = tau_data_wire[3];
346 amp_data_next = amp_data_wire[3];
347
348 // register 4th product
349 add_data_next[4] = add_data_wire;
350 out_data_next[4] = out_data_wire;
351
352 // register 4th output
353 out_data_next[0] = out_data_reg[1];
354
355 int_case_next = 3'd2;
356 end
357 default:
358 begin
359 int_case_next = 3'd0;
360 end
361 endcase
362 end
363
364 assign out_data = {out_data_reg[4], out_data_reg[3], out_data_reg[2], out_data_reg[0]};
365
366endmodule
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