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1 | module analyser
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2 | (
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3 | input wire clk, reset,
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4 | input wire data_ready,
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5 | input wire [1:0] uwt_flag,
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6 | output wire peak_ready
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7 | );
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8 |
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9 | reg flag_reg, flag_next;
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10 | reg [1:0] state_reg, state_next;
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11 | reg [4:0] counter_reg, counter_next;
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12 | reg peak_ready_reg;
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13 |
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14 | wire counter_max = (&counter_reg);
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15 | wire peak_ready_int = (flag_reg & data_ready & uwt_flag[0] & counter_max);
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16 |
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17 | always @(posedge clk)
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18 | begin
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19 | if (reset)
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20 | begin
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21 | flag_reg <= 1'b0;
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22 | state_reg <= 2'd0;
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23 | counter_reg <= 5'd0;
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24 | end
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25 | else
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26 | begin
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27 | flag_reg <= flag_next;
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28 | state_reg <= state_next;
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29 | counter_reg <= counter_next;
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30 | end
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31 | end
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32 |
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33 | always @*
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34 | begin
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35 | flag_next = flag_reg;
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36 | state_next = state_reg;
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37 | counter_next = counter_reg;
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38 | case (state_reg)
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39 | 0: // skip first 16 samples
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40 | begin
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41 | flag_next = 1'b0;
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42 | if (data_ready)
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43 | begin
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44 | counter_next = counter_reg + 5'd1;
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45 | if (counter_max)
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46 | begin
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47 | state_next = 2'd1;
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48 | end
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49 | end
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50 | end
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51 |
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52 | 1: // skip first 16 minima
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53 | begin
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54 | flag_next = 1'b0;
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55 | if (data_ready & uwt_flag[1])
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56 | begin
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57 | counter_next = counter_reg + 5'd1;
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58 | if (counter_max)
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59 | begin
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60 | state_next = 2'd2;
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61 | end
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62 | end
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63 | end
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64 |
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65 | 2:
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66 | begin
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67 | flag_next = 1'b1;
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68 | if (data_ready)
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69 | begin
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70 | if (~counter_max)
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71 | begin
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72 | counter_next = counter_reg + 5'd1;
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73 | end
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74 | if (peak_ready_int)
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75 | begin
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76 | counter_next = 5'd0;
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77 | end
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78 | end
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79 | end
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80 |
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81 | default:
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82 | begin
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83 | flag_next = 1'b0;
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84 | state_next = 2'd0;
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85 | counter_next = 5'd0;
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86 | end
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87 | endcase
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88 | end
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89 |
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90 | assign peak_ready = peak_ready_int;
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91 |
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92 | endmodule
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