source: trunk/MultiChannelUSB/analyser.v@ 81

Last change on this file since 81 was 76, checked in by demin, 15 years ago

add counter between peaks

File size: 1.7 KB
Line 
1module analyser
2 (
3 input wire clk, reset,
4 input wire data_ready,
5 input wire [1:0] uwt_flag,
6 output wire peak_ready
7 );
8
9 reg [1:0] state_reg, state_next;
10 reg [3:0] counter_reg, counter_next;
11 reg peak_ready_reg, peak_ready_next;
12
13 wire counter_max = (&counter_reg);
14
15 always @(posedge clk)
16 begin
17 if (reset)
18 begin
19 state_reg <= 2'd0;
20 counter_reg <= 4'd0;
21 peak_ready_reg <= 1'b0;
22 end
23 else
24 begin
25 state_reg <= state_next;
26 counter_reg <= counter_next;
27 peak_ready_reg <= peak_ready_next;
28 end
29 end
30
31 always @*
32 begin
33 state_next = state_reg;
34 counter_next = counter_reg;
35 peak_ready_next = peak_ready_reg;
36 case (state_reg)
37 0: // skip first 16 samples
38 begin
39 peak_ready_next = 1'b0;
40 if (data_ready)
41 begin
42 counter_next = counter_reg + 4'd1;
43 if (counter_max)
44 begin
45 state_next = 2'd1;
46 end
47 end
48 end
49
50 1: // skip first 16 minima
51 begin
52 if (data_ready & uwt_flag[1])
53 begin
54 counter_next = counter_reg + 4'd1;
55 if (counter_max)
56 begin
57 state_next = 2'd2;
58 end
59 end
60 end
61
62 2:
63 begin
64 if (data_ready & uwt_flag[0] & counter_max)
65 begin
66 counter_next = 4'd0;
67 peak_ready_next = 1'b1;
68 end
69 else
70 begin
71 if (~counter_max)
72 begin
73 counter_next = counter_reg + 4'd1;
74 end
75 peak_ready_next = 1'b0;
76 end
77 end
78
79 default:
80 begin
81 state_next = 2'd0;
82 counter_next = 4'd0;
83 peak_ready_next = 1'b0;
84 end
85 endcase
86 end
87
88 assign peak_ready = peak_ready_reg;
89endmodule
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