source: trunk/MultiChannelUSB/analyser.v@ 106

Last change on this file since 106 was 100, checked in by demin, 15 years ago

multiple fixes
File size: 3.5 KB
Line 
1module analyser
2 (
3 input wire clock, frame, reset,
4 input wire [24:0] cfg_data,
5 input wire [1:0] uwt_flag,
6 input wire [11:0] uwt_data,
7 output wire ana_dead,
8 output wire ana_good,
9 output wire [11:0] ana_data,
10 output wire [11:0] ana_base
11 );
12
13 reg [2:0] state_reg, state_next;
14 reg [4:0] counter_reg, counter_next;
15 reg dead_reg, dead_next;
16 reg good_reg, good_next;
17 reg [11:0] data_reg, data_next;
18
19 reg [19:0] sample_reg, sample_next;
20
21 reg [19:0] buffer_reg [31:0];
22 reg [19:0] buffer_next [31:0];
23
24 wire [11:0] baseline = buffer_reg[31][16:5];
25 wire counter_max = (&counter_reg);
26
27 integer i;
28
29 always @(posedge clock)
30 begin
31 if (reset)
32 begin
33 state_reg <= 3'd0;
34 counter_reg <= 5'd0;
35 sample_reg = 20'd0;
36 dead_reg <= 1'b0;
37 good_reg <= 1'b0;
38 data_reg <= 12'd0;
39
40 for (i = 0; i <= 31; i = i + 1)
41 begin
42 buffer_reg[i] <= 20'hfffff;
43 end
44 end
45 else
46 begin
47 state_reg <= state_next;
48 counter_reg <= counter_next;
49 sample_reg <= sample_next;
50 dead_reg <= dead_next;
51 good_reg <= good_next;
52 data_reg <= data_next;
53
54 for (i = 0; i <= 31; i = i + 1)
55 begin
56 buffer_reg[i] <= buffer_next[i];
57 end
58 end
59 end
60
61 always @*
62 begin
63 state_next = state_reg;
64 counter_next = counter_reg;
65 sample_next = sample_reg;
66 dead_next = dead_reg;
67 good_next = good_reg;
68 data_next = data_reg;
69
70 for (i = 0; i <= 31; i = i + 1)
71 begin
72 buffer_next[i] = buffer_reg[i];
73 end
74
75 case (state_reg)
76 0: // skip first 32 samples
77 begin
78 if (frame)
79 begin
80 counter_next = counter_reg + 5'd1;
81 if (counter_max)
82 begin
83 state_next = 3'd1;
84 end
85 end
86 end
87
88 1: // skip first 32 baseline samples
89 begin
90 if (frame)
91 begin
92 for (i = 0; i < 31; i = i + 1)
93 begin
94 buffer_next[i+1] = buffer_reg[i] + {8'd0, uwt_data};
95 end
96 buffer_next[0] = {8'd0, uwt_data};
97
98 counter_next = counter_reg + 5'd1;
99 if (counter_max)
100 begin
101 state_next = 3'd2;
102 end
103 end
104 end
105
106 2:
107 begin
108 if (frame)
109 begin
110
111 if (cfg_data[24])
112 begin
113 if (uwt_data > baseline)
114 begin
115 data_next = uwt_data - baseline;
116 end
117 else
118 begin
119 data_next = 12'd0;
120 end
121 end
122 else
123 begin
124 if (uwt_data > cfg_data[23:12])
125 begin
126 data_next = uwt_data - cfg_data[23:12];
127 end
128 else
129 begin
130 data_next = 12'd0;
131 end
132 end
133
134 sample_next = {8'd0, uwt_data};
135
136 dead_next = 1'b1;
137 good_next = 1'b0;
138
139 state_next = 3'd3;
140 end
141 end
142
143 3:
144 begin
145
146 // if (sample - baseline < threshold)
147 if (data_reg < cfg_data[11:0])
148 begin
149 for (i = 0; i < 31; i = i + 1)
150 begin
151 buffer_next[i+1] = buffer_reg[i] + sample_reg;
152 end
153 buffer_next[0] = sample_reg;
154 dead_next = 1'b0;
155 end
156
157 state_next = 3'd2;
158
159 // skip 32 samples after peak
160 if (counter_max)
161 begin
162 if (uwt_flag[0])
163 begin
164 counter_next = 5'd0;
165 state_next = 3'd4;
166 end
167 end
168 else
169 begin
170 counter_next = counter_reg + 5'd1;
171 end
172 end
173
174 4:
175 begin
176 good_next = dead_reg;
177 state_next = 2'd2;
178 end
179 endcase
180 end
181
182 assign ana_dead = dead_reg;
183 assign ana_good = good_reg;
184 assign ana_data = data_reg;
185 assign ana_base = baseline;
186
187endmodule
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