Last change
on this file since 143 was 60, checked in by demin, 15 years ago |
interface for parallel ADC with unreliable clock
|
File size:
595 bytes
|
Line | |
---|
1 | module adc_para
|
---|
2 | (
|
---|
3 | input wire lvds_dco,
|
---|
4 | input wire lvds_fco,
|
---|
5 | input wire para_data_ready,
|
---|
6 | input wire [11:0] para_data,
|
---|
7 |
|
---|
8 | output wire [11:0] adc_data
|
---|
9 | );
|
---|
10 |
|
---|
11 | reg [1:0] int_data_ready;
|
---|
12 | reg [11:0] int_data, int_adc_data;
|
---|
13 |
|
---|
14 | always @ (posedge lvds_dco)
|
---|
15 | begin
|
---|
16 | int_data_ready[1] <= int_data_ready[0];
|
---|
17 | int_data_ready[0] <= para_data_ready;
|
---|
18 | if ((int_data_ready[0]) & (~int_data_ready[1]))
|
---|
19 | begin
|
---|
20 | int_data <= para_data;
|
---|
21 | end
|
---|
22 | end
|
---|
23 |
|
---|
24 | always @ (posedge lvds_fco)
|
---|
25 | begin
|
---|
26 | int_adc_data <= int_data;
|
---|
27 | end
|
---|
28 |
|
---|
29 | assign adc_data = int_adc_data;
|
---|
30 |
|
---|
31 | endmodule
|
---|
Note:
See
TracBrowser
for help on using the repository browser.