Last change
on this file since 151 was 60, checked in by demin, 15 years ago |
interface for parallel ADC with unreliable clock
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File size:
595 bytes
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Rev | Line | |
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[60] | 1 | module adc_para
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| 2 | (
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| 3 | input wire lvds_dco,
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| 4 | input wire lvds_fco,
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| 5 | input wire para_data_ready,
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| 6 | input wire [11:0] para_data,
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| 7 |
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| 8 | output wire [11:0] adc_data
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| 9 | );
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| 10 |
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| 11 | reg [1:0] int_data_ready;
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| 12 | reg [11:0] int_data, int_adc_data;
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| 13 |
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| 14 | always @ (posedge lvds_dco)
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| 15 | begin
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| 16 | int_data_ready[1] <= int_data_ready[0];
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| 17 | int_data_ready[0] <= para_data_ready;
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| 18 | if ((int_data_ready[0]) & (~int_data_ready[1]))
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| 19 | begin
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| 20 | int_data <= para_data;
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| 21 | end
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| 22 | end
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| 23 |
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| 24 | always @ (posedge lvds_fco)
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| 25 | begin
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| 26 | int_adc_data <= int_data;
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| 27 | end
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| 28 |
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| 29 | assign adc_data = int_adc_data;
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| 30 |
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| 31 | endmodule
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