Last change
on this file since 75 was 72, checked in by demin, 15 years ago |
testing all components together
|
File size:
1.4 KB
|
Line | |
---|
1 | module adc_lvds
|
---|
2 | #(
|
---|
3 | parameter size = 3, // number of channels
|
---|
4 | parameter width = 12 // channel resolution
|
---|
5 | )
|
---|
6 | (
|
---|
7 | input wire lvds_dco,
|
---|
8 | input wire lvds_fco,
|
---|
9 | input wire [size-1:0] lvds_d,
|
---|
10 |
|
---|
11 | output wire [size*width-1:0] adc_data
|
---|
12 | );
|
---|
13 |
|
---|
14 | wire [size-1:0] int_data_h, int_data_l;
|
---|
15 | reg [width-1:0] int_data_next [size-1:0];
|
---|
16 | reg [width-1:0] int_data_reg [size-1:0];
|
---|
17 |
|
---|
18 | reg [width-1:0] int_adc_data [size-1:0];
|
---|
19 |
|
---|
20 | integer i;
|
---|
21 | genvar j;
|
---|
22 |
|
---|
23 | altddio_in #(
|
---|
24 | .intended_device_family("Cyclone III"),
|
---|
25 | .invert_input_clocks("ON"),
|
---|
26 | .lpm_type("altddio_in"),
|
---|
27 | .width(size)) altddio_in_unit (
|
---|
28 | .datain(lvds_d),
|
---|
29 | .inclock(lvds_dco),
|
---|
30 | .aclr(1'b0),
|
---|
31 | .dataout_h(int_data_h),
|
---|
32 | .dataout_l(int_data_l),
|
---|
33 | .aset(1'b0),
|
---|
34 | .inclocken(1'b1),
|
---|
35 | .sclr(1'b0),
|
---|
36 | .sset(1'b0));
|
---|
37 |
|
---|
38 | always @ (posedge lvds_dco)
|
---|
39 | begin
|
---|
40 | for (i = 0; i < size; i = i + 1)
|
---|
41 | begin
|
---|
42 | int_data_reg[i] <= int_data_next[i];
|
---|
43 | end
|
---|
44 | end
|
---|
45 |
|
---|
46 | always @ (posedge lvds_fco)
|
---|
47 | begin
|
---|
48 | for (i = 0; i < size; i = i + 1)
|
---|
49 | begin
|
---|
50 | int_adc_data[i] <= int_data_next[i];
|
---|
51 | end
|
---|
52 | end
|
---|
53 |
|
---|
54 | always @*
|
---|
55 | begin
|
---|
56 | for (i = 0; i < size; i = i + 1)
|
---|
57 | begin
|
---|
58 | int_data_next[i] = {int_data_reg[i][9:0], int_data_l[i], int_data_h[i]};
|
---|
59 | end
|
---|
60 | end
|
---|
61 |
|
---|
62 | generate
|
---|
63 | for (j = 0; j < size; j = j + 1)
|
---|
64 | begin : ADC_LVDS_OUTPUT
|
---|
65 | assign adc_data[j*width+width-1:j*width] = int_adc_data[j];
|
---|
66 | end
|
---|
67 | endgenerate
|
---|
68 |
|
---|
69 | endmodule
|
---|
Note:
See
TracBrowser
for help on using the repository browser.