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[41] | 1 | module adc_lvds
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| 2 | (
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| 3 | input wire lvds_dco,
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| 4 | input wire lvds_fco,
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| 5 | input wire [2:0] lvds_d,
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| 6 |
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| 7 | output wire adc_clk,
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| 8 | output wire [11:0] adc_db,
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| 9 | output wire [11:0] adc_dc,
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| 10 | output wire [11:0] adc_dd
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| 11 | );
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| 12 |
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| 13 |
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| 14 | wire [2:0] int_data_h, int_data_l;
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| 15 | reg [11:0] int_data_sr [2:0];
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| 16 | reg [11:0] int_data [2:0];
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| 17 | reg int_fco;
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| 18 |
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| 19 | integer i;
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| 20 |
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| 21 | altddio_in #(
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| 22 | .intended_device_family("Cyclone III"),
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| 23 | .invert_input_clocks("OFF"),
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| 24 | .lpm_type("altddio_in"),
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| 25 | .width(3)) altddio_in_unit (
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| 26 | .datain(lvds_d),
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| 27 | .inclock(lvds_dco),
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| 28 | .aclr(1'b0),
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| 29 | .dataout_h(int_data_h),
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| 30 | .dataout_l(int_data_l),
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| 31 | .aset(1'b0),
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| 32 | .inclocken(1'b1),
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| 33 | .sclr(1'b0),
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| 34 | .sset(1'b0));
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| 35 |
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| 36 | always @ (posedge lvds_dco)
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| 37 | begin
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| 38 | for(i = 0; i < 3; i = i + 1)
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| 39 | begin
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| 40 | int_data_sr[i] <= {int_data_sr[i][9:0], int_data_h[i], int_data_l[i]};
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| 41 | end
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| 42 |
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| 43 | // one clock delay for FCO
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| 44 | int_fco <= lvds_fco;
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| 45 |
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| 46 | if((lvds_fco) & (~int_fco))
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| 47 | begin
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| 48 | for(i = 0; i < 3; i = i + 1)
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| 49 | begin
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| 50 | int_data[i] <= {int_data_sr[i][9:0], int_data_h[i], int_data_l[i]};
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| 51 | end
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| 52 | end
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| 53 | end
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| 54 |
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| 55 | assign adc_clk = int_fco;
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| 56 | assign adc_db = int_data[0];
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| 57 | assign adc_dc = int_data[1];
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| 58 | assign adc_dd = int_data[2];
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| 59 |
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| 60 | endmodule
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