source: trunk/MultiChannelUSB/adc_fifo.v@ 76

Last change on this file since 76 was 72, checked in by demin, 15 years ago

testing all components together

File size: 1.4 KB
Line 
1module adc_fifo
2 (
3 input wire adc_clk,
4 input wire [11:0] adc_data,
5
6 input wire clk,
7 output wire data_ready,
8 output wire [11:0] data
9 );
10
11 wire [11:0] int_q;
12 reg [11:0] int_data;
13
14 reg state, int_rdreq, int_data_ready;
15 wire int_wrfull, int_rdempty;
16
17 dcfifo #(
18 .intended_device_family("Cyclone III"),
19 .lpm_numwords(16),
20 .lpm_showahead("ON"),
21 .lpm_type("dcfifo"),
22 .lpm_width(12),
23 .lpm_widthu(4),
24 .rdsync_delaypipe(4),
25 .wrsync_delaypipe(4),
26 .overflow_checking("ON"),
27 .underflow_checking("ON"),
28 .use_eab("OFF"),
29 .write_aclr_synch("OFF")) fifo_unit (
30 .aclr(1'b0),
31 .data(adc_data),
32 .rdclk(clk),
33 .rdreq((~int_rdempty) & int_rdreq),
34 .wrclk(adc_clk),
35 .wrreq(~int_wrfull),
36 .q(int_q),
37 .rdempty(int_rdempty),
38 .wrfull(int_wrfull),
39 .rdfull(),
40 .rdusedw(),
41 .wrempty(),
42 .wrusedw());
43
44 always @(posedge clk)
45 begin
46 case (state)
47 1'b0:
48 begin
49 int_rdreq <= 1'b1;
50 int_data_ready <= 1'b0;
51 state <= 1'b1;
52 end
53
54 1'b1:
55 begin
56 if (~int_rdempty)
57 begin
58 int_data <= int_q;
59 int_rdreq <= 1'b0;
60 int_data_ready <= 1'b1;
61 state <= 1'b0;
62 end
63 end
64
65 default:
66 begin
67 int_rdreq <= 1'b1;
68 int_data_ready <= 1'b0;
69 state <= 1'b1;
70 end
71 endcase
72 end
73
74 assign data_ready = int_data_ready;
75 assign data = int_data;
76
77endmodule
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