source: trunk/MultiChannelUSB/adc_fifo.v@ 47

Last change on this file since 47 was 45, checked in by demin, 15 years ago

add fourth channel and switch from 32 to 24 bit histogram
File size: 2.5 KB
Line 
1module adc_fifo
2 (
3 input wire adc_clk,
4 input wire [11:0] adc_data,
5
6 input wire aclr,
7 input wire rdclk,
8
9 output wire ready,
10 output wire [11:0] raw_data,
11 output wire [13:0] uwt_data
12 );
13
14 wire [31:0] uwt_d1, uwt_a1, uwt_peak1;
15 wire [31:0] uwt_d2, uwt_a2, uwt_peak2;
16 wire [31:0] uwt_d3, uwt_a3, uwt_peak3;
17 wire [1:0] uwt_flag1, uwt_flag2, uwt_flag3;
18
19 wire [1:0] wrfull;
20
21 reg state;
22 reg int_rdreq, int_ready;
23 wire int_rdempty;
24
25 uwt_bior31 #(.L(1)) uwt_1_unit (
26 .clk(adc_clk),
27 .x({20'h00000, adc_data}),
28 .d(uwt_d1),
29 .a(uwt_a1),
30 .peak(uwt_peak1),
31 .flag(uwt_flag1));
32
33 uwt_bior31 #(.L(2)) uwt_2_unit (
34 .clk(adc_clk),
35 .x(uwt_a1),
36 .d(uwt_d2),
37 .a(uwt_a2),
38 .peak(uwt_peak2),
39 .flag(uwt_flag2));
40
41 uwt_bior31 #(.L(3)) uwt_3_unit (
42 .clk(adc_clk),
43 .x(uwt_a2),
44 .d(uwt_d3),
45 .a(uwt_a3),
46 .peak(uwt_peak3),
47 .flag(uwt_flag3));
48
49 dcfifo #(
50 .intended_device_family("Cyclone III"),
51 .lpm_numwords(16),
52 .lpm_showahead("ON"),
53 .lpm_type("dcfifo"),
54 .lpm_width(12),
55 .lpm_widthu(4),
56 .rdsync_delaypipe(4),
57 .wrsync_delaypipe(4),
58 .overflow_checking("ON"),
59 .underflow_checking("ON"),
60 .use_eab("OFF"),
61 .write_aclr_synch("OFF")) fifo_raw (
62 .aclr(aclr),
63 .data(adc_data),
64 .rdclk(rdclk),
65 .rdreq(int_rdreq),
66 .wrclk(adc_clk),
67 .wrreq(~wrfull[0]),
68 .q(raw_data),
69 .rdempty(int_rdempty),
70 .wrfull(wrfull[0]),
71 .rdfull(),
72 .rdusedw(),
73 .wrempty(),
74 .wrusedw());
75
76 dcfifo #(
77 .intended_device_family("Cyclone III"),
78 .lpm_numwords(16),
79 .lpm_showahead("ON"),
80 .lpm_type("dcfifo"),
81 .lpm_width(14),
82 .lpm_widthu(4),
83 .rdsync_delaypipe(4),
84 .wrsync_delaypipe(4),
85 .overflow_checking("ON"),
86 .underflow_checking("ON"),
87 .use_eab("OFF"),
88 .write_aclr_synch("OFF")) fifo_uwt (
89 .aclr(aclr),
90 .data({uwt_flag3, uwt_peak3[11:0]}),
91 .rdclk(rdclk),
92 .rdreq(int_rdreq),
93 .wrclk(adc_clk),
94 .wrreq(~wrfull[1]),
95 .q(uwt_data),
96 .rdempty(),
97 .wrfull(wrfull[1]),
98 .rdfull(),
99 .rdusedw(),
100 .wrempty(),
101 .wrusedw());
102
103 always @ (posedge rdclk)
104 begin
105 case (state)
106 1'b0:
107 begin
108 if (~int_rdempty)
109 begin
110 int_rdreq <= 1'b1;
111 int_ready <= 1'b1;
112 state <= 1'b1;
113 end
114 end
115
116 1'b1:
117 begin
118 int_rdreq <= 1'b0;
119 int_ready <= 1'b0;
120 state <= 1'b0;
121 end
122
123 default:
124 begin
125 int_rdreq <= 1'b0;
126 int_ready <= 1'b0;
127 state <= 1'b0;
128 end
129 endcase
130 end
131
132 assign ready = int_ready;
133
134endmodule
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