source: trunk/MultiChannelUSB/Paella.v@ 79

Last change on this file since 79 was 75, checked in by demin, 15 years ago

fix osc_mux and trg_mux

File size: 11.8 KB
Line 
1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire I2C_SDA,
8 inout wire I2C_SCL,
9 inout wire [4:0] CON_A,
10 inout wire [15:0] CON_B,
11 input wire [12:0] CON_C,
12 input wire [1:0] CON_BCLK,
13 input wire [1:0] CON_CCLK,
14
15 input wire ADC_DCO,
16 input wire ADC_FCO,
17 input wire [2:0] ADC_D,
18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
45 localparam N = 3;
46
47 // Turn output ports off
48/*
49 assign RAM_CLK = 1'b0;
50 assign RAM_CE1 = 1'b0;
51 assign RAM_WE = 1'b0;
52 assign RAM_ADDR = 20'h00000;
53*/
54 assign RAM_CLK = CLK_50MHz;
55 assign RAM_CE1 = 1'b0;
56
57 // Turn inout ports to tri-state
58 assign TRG = 4'bz;
59 assign CON_A = 5'bz;
60 assign CON_B = 16'bz;
61 assign USB_PA0 = 1'bz;
62 assign USB_PA1 = 1'bz;
63 assign USB_PA3 = 1'bz;
64 assign USB_PA7 = 1'bz;
65// assign RAM_DQAP = 1'bz;
66// assign RAM_DQA = 8'bz;
67// assign RAM_DQBP = 1'bz;
68// assign RAM_DQB = 8'bz;
69
70 assign USB_PA2 = ~usb_rden;
71 assign USB_PA4 = usb_addr[0];
72 assign USB_PA5 = usb_addr[1];
73 assign USB_PA6 = ~usb_pktend;
74
75 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
76 wire usb_aclr;
77 wire usb_tx_wrreq, usb_rx_rdreq;
78 wire usb_tx_full, usb_rx_empty;
79 wire [7:0] usb_tx_data, usb_rx_data;
80 wire [1:0] usb_addr;
81
82 assign USB_SLRD = ~usb_rdreq;
83 assign USB_SLWR = ~usb_wrreq;
84
85 usb_fifo usb_unit
86 (
87 .usb_clk(USB_IFCLK),
88 .usb_data(USB_PB),
89 .usb_full(~USB_FLAGB),
90 .usb_empty(~USB_FLAGA),
91 .usb_wrreq(usb_wrreq),
92 .usb_rdreq(usb_rdreq),
93 .usb_rden(usb_rden),
94 .usb_pktend(usb_pktend),
95 .usb_addr(usb_addr),
96
97 .clk(CLK_50MHz),
98 .aclr(usb_aclr),
99
100 .tx_full(usb_tx_full),
101 .tx_wrreq(usb_tx_wrreq),
102 .tx_data(usb_tx_data),
103
104 .rx_empty(usb_rx_empty),
105 .rx_rdreq(usb_rx_rdreq),
106 .rx_q(usb_rx_data)
107 );
108
109 reg bln_reset [N-1:0];
110 wire [11:0] baseline [N-1:0];
111 wire [11:0] bln_baseline [N-1:0];
112
113 reg ana_reset [N-1:0];
114 wire ana_peak_ready [N-1:0];
115 wire [11:0] ana_peak [N-1:0];
116
117 reg osc_reset [N-1:0];
118 reg [9:0] osc_addr [N-1:0];
119 wire [9:0] osc_start_addr [N-1:0];
120 wire [15:0] osc_q [N-1:0];
121 wire osc_trig [N-1:0];
122
123 wire [3:0] osc_mux_sel [N-1:0];
124 wire [11:0] osc_mux_data [N-1:0];
125
126 wire trg_reset [N-1:0];
127 wire [3:0] trg_mux_sel [N-1:0];
128 wire [11:0] trg_mux_data [N-1:0];
129 wire [11:0] trg_thrs [N-1:0];
130
131 reg hst_reset [N-1:0];
132 reg [11:0] hst_addr [N-1:0];
133 wire hst_data_ready [N-1:0];
134 wire [11:0] hst_data [N-1:0];
135 wire [31:0] hst_q [N-1:0];
136
137
138 wire [3:0] hst_mux_sel [N-1:0];
139 wire [12:0] hst_mux_data [N-1:0];
140
141 wire [3:0] bln_mux_sel [N-1:0];
142 wire [11:0] bln_mux_data [N-1:0];
143
144 wire mux_reset, mux_type;
145 wire [1:0] mux_chan, mux_byte;
146 wire [15:0] mux_addr;
147
148 reg [7:0] mux_q;
149 reg [1:0] mux_max_byte;
150 reg [15:0] mux_min_addr, mux_max_addr;
151
152 wire adc_clk [N-1:0];
153 wire [11:0] adc_data [N-1:0];
154
155 wire data_ready [N-1:0];
156 wire [11:0] data [N-1:0];
157 wire [11:0] int_data [N-1:0];
158
159/*
160 assign osc_thrs[0] = 16'd40;
161 assign osc_thrs[1] = 16'd60;
162 assign osc_thrs[2] = 16'd40;
163 assign osc_thrs[3] = 16'd1650;
164*/
165 wire [31:0] uwt_d1 [N-1:0];
166 wire [31:0] uwt_a1 [N-1:0];
167 wire [31:0] uwt_peak1 [N-1:0];
168 wire [31:0] uwt_d2 [N-1:0];
169 wire [31:0] uwt_a2 [N-1:0];
170 wire [31:0] uwt_peak2 [N-1:0];
171 wire [31:0] uwt_d3 [N-1:0];
172 wire [31:0] uwt_a3 [N-1:0];
173 wire [31:0] uwt_peak3 [N-1:0];
174
175 wire [1:0] uwt_flag1 [N-1:0];
176 wire [1:0] uwt_flag2 [N-1:0];
177 wire [1:0] uwt_flag3 [N-1:0];
178
179 assign adc_clk[0] = ADC_FCO;
180 assign adc_clk[1] = ADC_FCO;
181// assign adc_clk[2] = ADC_FCO;
182/*
183 assign adc_clk[3] = ADC_FCO;
184*/
185/*
186 assign adc_clk[3] = CON_CCLK[0];
187 assign adc_data[3] = CON_C[11:0];
188*/
189/*
190 adc_para adc_para_unit (
191 .lvds_dco(ADC_DCO),
192 .lvds_fco(ADC_FCO),
193 .para_data_ready(CON_CCLK[0]),
194 .para_data(CON_C[11:0]),
195 .adc_data(adc_data[3]));
196*/
197/*
198 wire adc_pll_clk;
199
200 adc_pll adc_pll_unit(
201 .inclk0(ADC_FCO),
202 .c0(adc_pll_clk));
203*/
204
205 wire tst_adc_clk;
206 wire [11:0] tst_adc_data;
207
208 test test_unit(
209 .clk(CLK_50MHz),
210 .tst_clk(tst_adc_clk),
211 .tst_data(tst_adc_data));
212
213 assign adc_clk[2] = tst_adc_clk;
214 assign adc_data[2] = tst_adc_data;
215
216/*
217 altserial_flash_loader #(
218 .enable_shared_access("OFF"),
219 .enhanced_mode(1),
220 .intended_device_family("Cyclone III")) sfl_unit (
221 .noe(1'b0),
222 .asmi_access_granted(),
223 .asmi_access_request(),
224 .data0out(),
225 .dclkin(),
226 .scein(),
227 .sdoin());
228*/
229
230 adc_lvds #(
231 .size(2),
232 .width(12)) adc_lvds_unit (
233 .lvds_dco(ADC_DCO),
234// .lvds_dco(adc_pll_clk),
235 .lvds_fco(ADC_FCO),
236 .lvds_d(ADC_D[1:0]),
237 .adc_data({ adc_data[1],
238 adc_data[0] }));
239
240
241 reg [15:0] cfg_memory [31:0];
242 wire [15:0] cfg_src_data;
243 wire [15:0] cfg_src_addr, cfg_dst_data, cfg_dst_addr;
244
245 wire cfg_polarity [N-1:0];
246 wire [11:0] cfg_baseline [N-1:0];
247 wire [11:0] cfg_hst_threshold [N-1:0];
248 wire [11:0] cfg_trg_threshold [N-1:0];
249
250 wire cfg_reset;
251
252 integer j;
253
254 always @(posedge CLK_50MHz)
255 begin
256 if (cfg_reset)
257 begin
258 for(j = 0; j <= 31; j = j + 1)
259 begin
260 cfg_memory[j] <= 16'd0;
261 end
262 end
263 else
264 begin
265 cfg_memory[cfg_dst_addr[4:0]] <= cfg_dst_data;
266 end
267 end
268
269 genvar i;
270
271 generate
272 for (i = 0; i < N; i = i + 1)
273 begin : MCA_CHAIN
274
275 assign cfg_polarity[i] = cfg_memory[10][4*i];
276 assign cfg_baseline[i] = cfg_memory[11+i][11:0];
277 assign cfg_hst_threshold[i] = cfg_memory[14+i][11:0];
278 assign cfg_trg_threshold[i] = cfg_memory[17+i][11:0];
279
280 assign osc_mux_sel[i] = cfg_memory[20+i][3:0];
281 assign trg_mux_sel[i] = cfg_memory[20+i][7:4];
282
283 assign hst_mux_sel[i] = cfg_memory[23+i][3:0];
284 assign bln_mux_sel[i] = cfg_memory[23+i][7:4];
285
286 adc_fifo adc_fifo_unit (
287 .adc_clk(adc_clk[i]),
288 .adc_data(adc_data[i]),
289 .clk(CLK_50MHz),
290 .data_ready(data_ready[i]),
291 .data(int_data[i]));
292
293 assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]);
294
295 uwt_bior31 #(.L(1)) uwt_1_unit (
296 .clk(CLK_50MHz),
297 .data_ready(data_ready[i]),
298 .x({20'h00000, data[i]}),
299 .d(uwt_d1[i]),
300 .a(uwt_a1[i]),
301 .peak(uwt_peak1[i]),
302 .flag(uwt_flag1[i]));
303
304 uwt_bior31 #(.L(2)) uwt_2_unit (
305 .clk(CLK_50MHz),
306 .data_ready(data_ready[i]),
307 .x(uwt_a1[i]),
308 .d(uwt_d2[i]),
309 .a(uwt_a2[i]),
310 .peak(uwt_peak2[i]),
311 .flag(uwt_flag2[i]));
312
313 uwt_bior31 #(.L(3)) uwt_3_unit (
314 .clk(CLK_50MHz),
315 .data_ready(data_ready[i]),
316 .x(uwt_a2[i]),
317 .d(uwt_d3[i]),
318 .a(uwt_a3[i]),
319 .peak(uwt_peak3[i]),
320 .flag(uwt_flag3[i]));
321
322 lpm_mux #(
323 .lpm_size(5),
324 .lpm_type("LPM_MUX"),
325 .lpm_width(12),
326 .lpm_widths(3)) osc_mux_unit (
327 .sel(osc_mux_sel[i][2:0]),
328 .data({ bln_baseline[i],
329 uwt_a3[i][20:9],
330 uwt_a2[i][17:6],
331 uwt_a1[i][14:3],
332 data[i] }),
333 .result(osc_mux_data[i]));
334
335 lpm_mux #(
336 .lpm_size(5),
337 .lpm_type("LPM_MUX"),
338 .lpm_width(12),
339 .lpm_widths(3)) trg_mux_unit (
340 .sel(trg_mux_sel[i][2:0]),
341 .data({ bln_baseline[i],
342 uwt_a3[i][20:9],
343 uwt_a2[i][17:6],
344 uwt_a1[i][14:3],
345 data[i] }),
346 .result(trg_mux_data[i]));
347
348 lpm_mux #(
349 .lpm_size(2),
350 .lpm_type("LPM_MUX"),
351 .lpm_width(13),
352 .lpm_widths(1)) hst_mux_unit (
353 .sel(hst_mux_sel[i][0]),
354 .data({ {ana_peak[i], ana_peak_ready[i]},
355 {data[i], data_ready[i]} }),
356 .result(hst_mux_data[i]));
357
358 lpm_mux #(
359 .lpm_size(2),
360 .lpm_type("LPM_MUX"),
361 .lpm_width(12),
362 .lpm_widths(1)) bln_mux_unit (
363 .sel(bln_mux_sel[i][0]),
364 .data({bln_baseline[i], cfg_baseline[i]}),
365 .result(bln_mux_data[i]));
366
367 baseline baseline_unit (
368 .clk(CLK_50MHz),
369 .reset(bln_reset[i]),
370 .data_ready(data_ready[i]),
371 .uwt_flag(uwt_flag3[i]),
372 .uwt_data(uwt_peak3[i]),
373 .baseline(bln_baseline[i]));
374
375 analyser analyser_unit (
376 .clk(CLK_50MHz),
377 .reset(ana_reset[i]),
378 .data_ready(data_ready[i]),
379 .uwt_flag(uwt_flag3[i]),
380 .uwt_data(uwt_peak3[i]),
381 .peak_ready(ana_peak_ready[i]),
382 .peak(ana_peak[i]));
383
384 assign hst_data[i] = (hst_mux_data[i][12:1] > bln_mux_data[i]) ? (hst_mux_data[i][12:1] - bln_mux_data[i]) : 12'd0;
385 assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]);
386
387 histogram #(.W(32)) histogram_unit (
388 .clk(CLK_50MHz),
389 .reset(hst_reset[i]),
390 .data_ready(hst_data_ready[i]),
391 .data(hst_data[i]),
392 .address(hst_addr[i]),
393 .q(hst_q[i]));
394
395 trigger trigger_unit (
396 .clk(CLK_50MHz),
397 .reset(trg_reset[i]),
398 .data_ready(data_ready[i]),
399 .data(trg_mux_data[i]),
400 .threshold(cfg_trg_threshold[i]),
401 .trigger(osc_trig[i]));
402
403
404 oscilloscope oscilloscope_unit (
405 .clk(CLK_50MHz),
406 .reset(osc_reset[i]),
407 .data_ready(data_ready[i]),
408 .data(osc_mux_data[i]),
409 .trigger(osc_trig[i]),
410 .address(osc_addr[i]),
411 .start_address(osc_start_addr[i]),
412 .q(osc_q[i]));
413 end
414 endgenerate
415
416 always @*
417 begin
418 for (j = 0; j < N; j = j + 1)
419 begin
420 osc_reset[j] = 1'b0;
421 osc_addr[j] = 10'b0;
422 hst_reset[j] = 1'b0;
423 hst_addr[j] = 12'b0;
424 end
425
426 case(mux_type)
427// case({mux_type, mux_chan})
428 1'b0:
429// 3'b000, 3'b001, 3'b010, 3'b011:
430 begin
431 osc_reset[mux_chan] = mux_reset;
432 osc_addr[mux_chan] = mux_addr[9:0];
433 mux_max_byte = 2'd1;
434 mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
435 mux_max_addr = 16'd1023;
436 end
437
438 1'b1:
439// 3'b100, 3'b101, 3'b110, 3'b011:
440 begin
441 hst_reset[mux_chan] = mux_reset;
442 hst_addr[mux_chan] = mux_addr[11:0];
443 mux_max_byte = 2'd3;
444 mux_min_addr = 16'd0;
445 mux_max_addr = 16'd4095;
446 end
447 endcase
448 end
449
450 always @*
451 begin
452 case ({mux_type, mux_byte})
453 3'b000: mux_q = osc_q[mux_chan][7:0];
454 3'b001: mux_q = osc_q[mux_chan][15:8];
455
456 3'b100: mux_q = hst_q[mux_chan][7:0];
457 3'b101: mux_q = hst_q[mux_chan][15:8];
458 3'b110: mux_q = hst_q[mux_chan][23:16];
459 3'b111: mux_q = hst_q[mux_chan][31:24];
460
461 default: mux_q = 8'd0;
462 endcase
463 end
464
465 wire i2c_aclr;
466 wire i2c_wrreq;
467 wire i2c_full;
468 wire [15:0] i2c_data;
469
470 i2c_fifo i2c_unit(
471 .clk(CLK_50MHz),
472 .aclr(i2c_aclr),
473 .wrreq(i2c_wrreq),
474 .data(i2c_data),
475 .full(i2c_full),
476/*
477 normal connection
478 .i2c_sda(I2C_SDA),
479 .i2c_scl(I2C_SCL),
480
481 following is a cross wire connection for EPT
482*/
483 .i2c_sda(I2C_SCL),
484 .i2c_scl(I2C_SDA));
485
486 control control_unit (
487 .clk(CLK_50MHz),
488 .cfg_reset(cfg_reset),
489 .cfg_src_data(cfg_memory[cfg_src_addr[4:0]]),
490 .cfg_src_addr(cfg_src_addr),
491 .cfg_dst_data(cfg_dst_data),
492 .cfg_dst_addr(cfg_dst_addr),
493 .rx_empty(usb_rx_empty),
494 .tx_full(usb_tx_full),
495 .rx_data(usb_rx_data),
496 .mux_max_byte(mux_max_byte),
497 .mux_min_addr(mux_min_addr),
498 .mux_max_addr(mux_max_addr),
499 .mux_q(mux_q),
500 .mux_reset(mux_reset),
501 .mux_type(mux_type),
502 .mux_chan(mux_chan),
503 .mux_byte(mux_byte),
504 .mux_addr(mux_addr),
505 .rx_rdreq(usb_rx_rdreq),
506 .tx_wrreq(usb_tx_wrreq),
507 .tx_data(usb_tx_data),
508 .ram_we(RAM_WE),
509 .ram_addr(RAM_ADDR),
510 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
511 .i2c_wrreq(i2c_wrreq),
512 .i2c_data(i2c_data),
513 .i2c_full(i2c_full),
514 .led(LED));
515
516endmodule
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