source: trunk/MultiChannelUSB/Paella.v@ 87

Last change on this file since 87 was 86, checked in by demin, 15 years ago

replace 3 ADC FIFO with one large FIFO

File size: 11.6 KB
Line 
1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire I2C_SDA,
8 inout wire I2C_SCL,
9 inout wire [4:0] CON_A,
10 input wire [15:0] CON_B,
11 input wire [12:0] CON_C,
12 input wire [1:0] CON_BCLK,
13 input wire [1:0] CON_CCLK,
14
15 input wire ADC_DCO,
16 input wire ADC_FCO,
17 input wire [2:0] ADC_D,
18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
45 localparam N = 3;
46
47 // Turn output ports off
48/*
49 assign RAM_CLK = 1'b0;
50 assign RAM_CE1 = 1'b0;
51 assign RAM_WE = 1'b0;
52 assign RAM_ADDR = 20'h00000;
53*/
54 assign RAM_CLK = sys_clk;
55 assign RAM_CE1 = 1'b0;
56
57 // Turn inout ports to tri-state
58 assign TRG = 4'bz;
59 assign CON_A = 5'bz;
60 assign USB_PA0 = 1'bz;
61 assign USB_PA1 = 1'bz;
62 assign USB_PA3 = 1'bz;
63 assign USB_PA7 = 1'bz;
64// assign RAM_DQAP = 1'bz;
65// assign RAM_DQA = 8'bz;
66// assign RAM_DQBP = 1'bz;
67// assign RAM_DQB = 8'bz;
68
69 assign USB_PA2 = ~usb_rden;
70 assign USB_PA4 = usb_addr[0];
71 assign USB_PA5 = usb_addr[1];
72 assign USB_PA6 = ~usb_pktend;
73
74 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
75 wire usb_aclr;
76 wire usb_tx_wrreq, usb_rx_rdreq;
77 wire usb_tx_full, usb_rx_empty;
78 wire [7:0] usb_tx_data, usb_rx_data;
79 wire [1:0] usb_addr;
80
81 assign USB_SLRD = ~usb_rdreq;
82 assign USB_SLWR = ~usb_wrreq;
83
84 usb_fifo usb_unit
85 (
86 .usb_clk(USB_IFCLK),
87 .usb_data(USB_PB),
88 .usb_full(~USB_FLAGB),
89 .usb_empty(~USB_FLAGA),
90 .usb_wrreq(usb_wrreq),
91 .usb_rdreq(usb_rdreq),
92 .usb_rden(usb_rden),
93 .usb_pktend(usb_pktend),
94 .usb_addr(usb_addr),
95
96 .clk(sys_clk),
97 .aclr(usb_aclr),
98
99 .tx_full(usb_tx_full),
100 .tx_wrreq(usb_tx_wrreq),
101 .tx_data(usb_tx_data),
102
103 .rx_empty(usb_rx_empty),
104 .rx_rdreq(usb_rx_rdreq),
105 .rx_q(usb_rx_data)
106 );
107
108 reg bln_reset [N-1:0];
109 wire [11:0] baseline [N-1:0];
110 wire [11:0] bln_baseline [N-1:0];
111
112 reg ana_reset [N-1:0];
113 wire ana_peak_ready [N-1:0];
114 wire ana_peak_debug [N-1:0];
115
116 reg osc_reset [N-1:0];
117 reg [9:0] osc_addr [N-1:0];
118 wire [9:0] osc_start_addr [N-1:0];
119 wire [15:0] osc_q [N-1:0];
120 wire osc_trig [N-1:0];
121
122 wire [3:0] osc_mux_sel [N-1:0];
123 wire [11:0] osc_mux_data [N-1:0];
124
125 wire trg_reset [N-1:0];
126 wire [3:0] trg_mux_sel [N-1:0];
127 wire [11:0] trg_mux_data [N-1:0];
128 wire [11:0] trg_thrs [N-1:0];
129
130 reg hst_reset [N-1:0];
131 reg [11:0] hst_addr [N-1:0];
132 wire hst_data_ready [N-1:0];
133 wire [11:0] hst_data [N-1:0];
134 wire [31:0] hst_q [N-1:0];
135
136
137 wire [3:0] hst_mux_sel [N-1:0];
138 wire [12:0] hst_mux_data [N-1:0];
139
140 wire [3:0] bln_mux_sel [N-1:0];
141 wire [11:0] bln_mux_data [N-1:0];
142
143 wire mux_reset, mux_type;
144 wire [1:0] mux_chan, mux_byte;
145 wire [15:0] mux_addr;
146
147 reg [7:0] mux_q;
148 reg [1:0] mux_max_byte;
149 reg [15:0] mux_min_addr, mux_max_addr;
150
151 wire [11:0] adc_data [N-1:0];
152
153 wire data_ready;
154 wire [11:0] data [N-1:0];
155 wire [11:0] int_data [N-1:0];
156
157 wire [11:0] cmp_data;
158
159 wire [11:0] nowhere;
160
161 wire sys_clk;
162
163 wire [31:0] uwt_d1 [N-1:0];
164 wire [31:0] uwt_a1 [N-1:0];
165 wire [31:0] uwt_peak1 [N-1:0];
166 wire [31:0] uwt_d2 [N-1:0];
167 wire [31:0] uwt_a2 [N-1:0];
168 wire [31:0] uwt_peak2 [N-1:0];
169 wire [31:0] uwt_d3 [N-1:0];
170 wire [31:0] uwt_a3 [N-1:0];
171 wire [31:0] uwt_peak3 [N-1:0];
172
173 wire [1:0] uwt_flag1 [N-1:0];
174 wire [1:0] uwt_flag2 [N-1:0];
175 wire [1:0] uwt_flag3 [N-1:0];
176
177/*
178 adc_para adc_para_unit (
179 .lvds_dco(ADC_DCO),
180 .lvds_fco(ADC_FCO),
181 .para_data_ready(CON_CCLK[0]),
182 .para_data(CON_C[11:0]),
183 .adc_data(adc_data[2]));
184*/
185/*
186 wire adc_pll_clk;
187
188 adc_pll adc_pll_unit(
189 .inclk0(ADC_FCO),
190 .c0(adc_pll_clk));
191*/
192
193 sys_pll sys_pll_unit(
194 .inclk0(CLK_50MHz),
195 .c0(sys_clk));
196
197 test test_unit(
198 .clk(ADC_FCO),
199 .data(adc_data[2]));
200// .data(nowhere);
201
202 adc_lvds #(
203 .size(3),
204 .width(12)) adc_lvds_unit (
205 .lvds_dco(ADC_DCO),
206// .lvds_dco(adc_pll_clk),
207 .lvds_fco(ADC_FCO),
208 .lvds_d(ADC_D[2:0]),
209// .adc_data({ adc_data[2],
210 .adc_data({ nowhere,
211 adc_data[1],
212 adc_data[0] }));
213
214 reg [15:0] cfg_memory [31:0];
215 wire [15:0] cfg_src_data;
216 wire [15:0] cfg_src_addr, cfg_dst_data, cfg_dst_addr;
217
218 wire cfg_polarity [N-1:0];
219 wire [11:0] cfg_baseline [N-1:0];
220 wire [11:0] cfg_hst_threshold [N-1:0];
221 wire [11:0] cfg_trg_threshold [N-1:0];
222
223 wire cfg_reset;
224
225 integer j;
226
227 always @(posedge sys_clk)
228 begin
229 if (cfg_reset)
230 begin
231 for(j = 0; j <= 31; j = j + 1)
232 begin
233 cfg_memory[j] <= 16'd0;
234 end
235 end
236 else
237 begin
238 cfg_memory[cfg_dst_addr[4:0]] <= cfg_dst_data;
239 end
240 end
241
242 adc_fifo #(.W(48)) adc_fifo_unit (
243 .adc_clk(ADC_FCO),
244 .adc_data({CON_B[11:0], adc_data[2], adc_data[1], adc_data[0]}),
245 .clk(sys_clk),
246 .data_ready(data_ready),
247 .data({cmp_data, int_data[2], int_data[1], int_data[0]}));
248
249 genvar i;
250
251 generate
252 for (i = 0; i < N; i = i + 1)
253 begin : MCA_CHAIN
254
255 assign cfg_polarity[i] = cfg_memory[10][4*i];
256 assign cfg_baseline[i] = cfg_memory[11+i][11:0];
257 assign cfg_hst_threshold[i] = cfg_memory[14+i][11:0];
258 assign cfg_trg_threshold[i] = cfg_memory[17+i][11:0];
259
260 assign osc_mux_sel[i] = cfg_memory[20+i][3:0];
261 assign trg_mux_sel[i] = cfg_memory[20+i][7:4];
262
263 assign hst_mux_sel[i] = cfg_memory[23+i][3:0];
264 assign bln_mux_sel[i] = cfg_memory[23+i][7:4];
265
266 assign data[i] = (cfg_polarity[i]) ? (int_data[i] ^ 12'hfff) : (int_data[i]);
267
268 uwt_bior31 #(.L(1)) uwt_1_unit (
269 .clk(sys_clk),
270 .data_ready(data_ready),
271 .x({20'h00000, data[i]}),
272 .d(uwt_d1[i]),
273 .a(uwt_a1[i]),
274 .peak(uwt_peak1[i]),
275 .flag(uwt_flag1[i]));
276
277 uwt_bior31 #(.L(2)) uwt_2_unit (
278 .clk(sys_clk),
279 .data_ready(data_ready),
280 .x(uwt_a1[i]),
281 .d(uwt_d2[i]),
282 .a(uwt_a2[i]),
283 .peak(uwt_peak2[i]),
284 .flag(uwt_flag2[i]));
285
286 uwt_bior31 #(.L(3)) uwt_3_unit (
287 .clk(sys_clk),
288 .data_ready(data_ready),
289 .x(uwt_a2[i]),
290 .d(uwt_d3[i]),
291 .a(uwt_a3[i]),
292 .peak(uwt_peak3[i]),
293 .flag(uwt_flag3[i]));
294
295 lpm_mux #(
296 .lpm_size(7),
297 .lpm_type("LPM_MUX"),
298 .lpm_width(12),
299 .lpm_widths(3)) osc_mux_unit (
300 .sel(osc_mux_sel[i][2:0]),
301 .data({ {ana_peak_debug[i], 11'd0},
302 hst_data[i],
303// uwt_d3[i][11:0],
304 bln_baseline[i],
305 uwt_a3[i][20:9],
306 uwt_a2[i][17:6],
307 uwt_a1[i][14:3],
308 data[i] }),
309 .result(osc_mux_data[i]));
310
311 lpm_mux #(
312 .lpm_size(7),
313 .lpm_type("LPM_MUX"),
314 .lpm_width(12),
315 .lpm_widths(3)) trg_mux_unit (
316 .sel(trg_mux_sel[i][2:0]),
317 .data({ {ana_peak_ready[i], 11'd0},
318 hst_data[i],
319// uwt_d3[i][11:0],
320 bln_baseline[i],
321 uwt_a3[i][20:9],
322 uwt_a2[i][17:6],
323 uwt_a1[i][14:3],
324 data[i] }),
325 .result(trg_mux_data[i]));
326
327 lpm_mux #(
328 .lpm_size(2),
329 .lpm_type("LPM_MUX"),
330 .lpm_width(13),
331 .lpm_widths(1)) hst_mux_unit (
332 .sel(hst_mux_sel[i][0]),
333 .data({ {uwt_peak3[i][11:0], ana_peak_ready[i]},
334 {data[i], data_ready} }),
335 .result(hst_mux_data[i]));
336
337 lpm_mux #(
338 .lpm_size(2),
339 .lpm_type("LPM_MUX"),
340 .lpm_width(12),
341 .lpm_widths(1)) bln_mux_unit (
342 .sel(bln_mux_sel[i][0]),
343 .data({bln_baseline[i], cfg_baseline[i]}),
344 .result(bln_mux_data[i]));
345
346 baseline baseline_unit (
347 .clk(sys_clk),
348 .reset(bln_reset[i]),
349 .data_ready(data_ready),
350 .uwt_flag(uwt_flag3[i]),
351 .uwt_data(uwt_peak3[i]),
352 .baseline(bln_baseline[i]));
353
354 analyser analyser_unit (
355 .clk(sys_clk),
356 .reset(ana_reset[i]),
357 .data_ready(data_ready),
358 .uwt_flag(uwt_flag3[i]),
359 .peak_ready(ana_peak_ready[i]),
360 .peak_debug(ana_peak_debug[i]));
361
362 suppression suppression_unit (
363 .clk(sys_clk),
364 .data(hst_mux_data[i][12:1]),
365 .baseline(bln_mux_data[i]),
366 .result(hst_data[i]));
367
368 assign hst_data_ready[i] = (hst_mux_data[i][0]) & (hst_data[i] >= cfg_hst_threshold[i]);
369
370 histogram #(.W(32)) histogram_unit (
371 .clk(sys_clk),
372 .reset(hst_reset[i]),
373 .data_ready(hst_data_ready[i]),
374 .data(hst_data[i]),
375 .address(hst_addr[i]),
376 .q(hst_q[i]));
377
378 trigger trigger_unit (
379 .clk(sys_clk),
380 .reset(trg_reset[i]),
381 .data_ready(data_ready),
382 .data(trg_mux_data[i]),
383 .threshold(cfg_trg_threshold[i]),
384 .trigger(osc_trig[i]));
385
386
387 oscilloscope oscilloscope_unit (
388 .clk(sys_clk),
389 .reset(osc_reset[i]),
390 .data_ready(data_ready),
391 .data(osc_mux_data[i]),
392 .trigger(osc_trig[i]),
393 .address(osc_addr[i]),
394 .start_address(osc_start_addr[i]),
395 .q(osc_q[i]));
396 end
397 endgenerate
398
399 always @*
400 begin
401 for (j = 0; j < N; j = j + 1)
402 begin
403 osc_reset[j] = 1'b0;
404 osc_addr[j] = 10'b0;
405 hst_reset[j] = 1'b0;
406 hst_addr[j] = 12'b0;
407 end
408
409 case(mux_type)
410 1'b0:
411 begin
412 osc_reset[mux_chan] = mux_reset;
413 osc_addr[mux_chan] = mux_addr[9:0];
414 mux_max_byte = 2'd1;
415 mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
416 mux_max_addr = 16'd1023;
417 end
418
419 1'b1:
420 begin
421 hst_reset[mux_chan] = mux_reset;
422 hst_addr[mux_chan] = mux_addr[11:0];
423 mux_max_byte = 2'd3;
424 mux_min_addr = 16'd0;
425 mux_max_addr = 16'd4095;
426 end
427 endcase
428 end
429
430 always @*
431 begin
432 case ({mux_type, mux_byte})
433 3'b000: mux_q = osc_q[mux_chan][7:0];
434 3'b001: mux_q = osc_q[mux_chan][15:8];
435
436 3'b100: mux_q = hst_q[mux_chan][7:0];
437 3'b101: mux_q = hst_q[mux_chan][15:8];
438 3'b110: mux_q = hst_q[mux_chan][23:16];
439 3'b111: mux_q = hst_q[mux_chan][31:24];
440
441 default: mux_q = 8'd0;
442 endcase
443 end
444
445 wire i2c_aclr;
446 wire i2c_wrreq;
447 wire i2c_full;
448 wire [15:0] i2c_data;
449
450 i2c_fifo i2c_unit(
451 .clk(sys_clk),
452 .aclr(i2c_aclr),
453 .wrreq(i2c_wrreq),
454 .data(i2c_data),
455 .full(i2c_full),
456/*
457 normal connection
458 .i2c_sda(I2C_SDA),
459 .i2c_scl(I2C_SCL),
460
461 following is a cross wire connection for EPT
462*/
463 .i2c_sda(I2C_SCL),
464 .i2c_scl(I2C_SDA));
465
466 control control_unit (
467 .clk(sys_clk),
468 .cfg_reset(cfg_reset),
469 .cfg_src_data(cfg_memory[cfg_src_addr[4:0]]),
470 .cfg_src_addr(cfg_src_addr),
471 .cfg_dst_data(cfg_dst_data),
472 .cfg_dst_addr(cfg_dst_addr),
473 .rx_empty(usb_rx_empty),
474 .tx_full(usb_tx_full),
475 .rx_data(usb_rx_data),
476 .mux_max_byte(mux_max_byte),
477 .mux_min_addr(mux_min_addr),
478 .mux_max_addr(mux_max_addr),
479 .mux_q(mux_q),
480 .mux_reset(mux_reset),
481 .mux_type(mux_type),
482 .mux_chan(mux_chan),
483 .mux_byte(mux_byte),
484 .mux_addr(mux_addr),
485 .rx_rdreq(usb_rx_rdreq),
486 .tx_wrreq(usb_tx_wrreq),
487 .tx_data(usb_tx_data),
488 .ram_we(RAM_WE),
489 .ram_addr(RAM_ADDR),
490 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
491 .ept_data_ready(data_ready),
492 .ept_data({cmp_data, data[2], data[1], data[0]}),
493 .i2c_wrreq(i2c_wrreq),
494 .i2c_data(i2c_data),
495 .i2c_full(i2c_full),
496 .led(LED));
497
498/*
499 altserial_flash_loader #(
500 .enable_shared_access("OFF"),
501 .enhanced_mode(1),
502 .intended_device_family("Cyclone III")) sfl_unit (
503 .noe(1'b0),
504 .asmi_access_granted(),
505 .asmi_access_request(),
506 .data0out(),
507 .dclkin(),
508 .scein(),
509 .sdoin());
510*/
511
512endmodule
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