source: trunk/MultiChannelUSB/Paella.v@ 70

Last change on this file since 70 was 70, checked in by demin, 15 years ago

intermediate working version with 32 bit histograms, test block and I2C master
File size: 7.9 KB
Line 
1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire I2C_SDA,
8 output wire I2C_SCL,
9 inout wire [4:0] CON_A,
10 inout wire [15:0] CON_B,
11 input wire [12:0] CON_C,
12 input wire [1:0] CON_BCLK,
13 input wire [1:0] CON_CCLK,
14
15 input wire ADC_DCO,
16 input wire ADC_FCO,
17 input wire [2:0] ADC_D,
18
19 output wire USB_SLRD,
20 output wire USB_SLWR,
21 input wire USB_IFCLK,
22 input wire USB_FLAGA, // EMPTY flag for EP6
23 input wire USB_FLAGB, // FULL flag for EP8
24 input wire USB_FLAGC,
25 inout wire USB_PA0,
26 inout wire USB_PA1,
27 output wire USB_PA2,
28 inout wire USB_PA3,
29 output wire USB_PA4,
30 output wire USB_PA5,
31 output wire USB_PA6,
32 inout wire USB_PA7,
33 inout wire [7:0] USB_PB,
34
35 output wire RAM_CLK,
36 output wire RAM_CE1,
37 output wire RAM_WE,
38 output wire [19:0] RAM_ADDR,
39 inout wire RAM_DQAP,
40 inout wire [7:0] RAM_DQA,
41 inout wire RAM_DQBP,
42 inout wire [7:0] RAM_DQB
43 );
44
45 // Turn output ports off
46/*
47 assign RAM_CLK = 1'b0;
48 assign RAM_CE1 = 1'b0;
49 assign RAM_WE = 1'b0;
50 assign RAM_ADDR = 20'h00000;
51*/
52 assign RAM_CLK = CLK_50MHz;
53 assign RAM_CE1 = 1'b0;
54
55 // Turn inout ports to tri-state
56 assign TRG = 4'bz;
57 assign CON_A = 5'bz;
58 assign CON_B = 16'bz;
59 assign USB_PA0 = 1'bz;
60 assign USB_PA1 = 1'bz;
61 assign USB_PA3 = 1'bz;
62 assign USB_PA7 = 1'bz;
63// assign RAM_DQAP = 1'bz;
64// assign RAM_DQA = 8'bz;
65// assign RAM_DQBP = 1'bz;
66// assign RAM_DQB = 8'bz;
67
68 assign USB_PA2 = ~usb_rden;
69 assign USB_PA4 = usb_addr[0];
70 assign USB_PA5 = usb_addr[1];
71 assign USB_PA6 = ~usb_pktend;
72
73 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
74 wire usb_aclr;
75 wire usb_tx_wrreq, usb_rx_rdreq;
76 wire usb_tx_full, usb_rx_empty;
77 wire [7:0] usb_tx_data, usb_rx_data;
78 wire [1:0] usb_addr;
79
80 assign USB_SLRD = ~usb_rdreq;
81 assign USB_SLWR = ~usb_wrreq;
82
83 usb_fifo usb_unit
84 (
85 .usb_clk(USB_IFCLK),
86 .usb_data(USB_PB),
87 .usb_full(~USB_FLAGB),
88 .usb_empty(~USB_FLAGA),
89 .usb_wrreq(usb_wrreq),
90 .usb_rdreq(usb_rdreq),
91 .usb_rden(usb_rden),
92 .usb_pktend(usb_pktend),
93 .usb_addr(usb_addr),
94
95 .clk(CLK_50MHz),
96 .aclr(usb_aclr),
97
98 .tx_full(usb_tx_full),
99 .tx_wrreq(usb_tx_wrreq),
100 .tx_data(usb_tx_data),
101
102 .rx_empty(usb_rx_empty),
103 .rx_rdreq(usb_rx_rdreq),
104 .rx_q(usb_rx_data)
105 );
106
107 reg ana_reset [3:0];
108 wire ana_peak_ready [3:0];
109 wire [11:0] ana_peak [3:0];
110
111 reg osc_reset [3:0];
112 reg [9:0] osc_addr [3:0];
113 wire [9:0] osc_start_addr [3:0];
114 wire [15:0] osc_q [3:0];
115
116 reg hst_reset [3:0];
117 reg [11:0] hst_addr [3:0];
118 wire [31:0] hst_q [3:0];
119
120 wire mux_reset, mux_type;
121 wire [1:0] mux_chan, mux_byte;
122 wire [15:0] mux_addr;
123
124 reg [7:0] mux_q;
125 reg [1:0] mux_max_byte;
126 reg [15:0] mux_min_addr, mux_max_addr;
127
128 wire adc_clk [3:0];
129 wire adc_data_ready [3:0];
130 wire [11:0] adc_data [3:0];
131
132 wire [11:0] raw_data [3:0];
133 wire [11:0] uwt_data [3:0];
134 wire [1:0] uwt_flag [3:0];
135
136 wire [16:0] osc_thrs [3:0];
137 wire adc_pola [3:0];
138
139 assign osc_thrs[0] = 16'd40;
140 assign osc_thrs[1] = 16'd60;
141 assign osc_thrs[2] = 16'd40;
142 assign osc_thrs[3] = 16'd1650;
143
144 assign adc_pola[0] = 1'b1;
145 assign adc_pola[1] = 1'b1;
146 assign adc_pola[2] = 1'b1;
147 assign adc_pola[3] = 1'b0;
148
149 assign adc_clk[0] = ADC_FCO;
150 assign adc_clk[1] = ADC_FCO;
151// assign adc_clk[2] = ADC_FCO;
152
153 assign adc_clk[3] = ADC_FCO;
154/*
155 assign adc_clk[3] = CON_CCLK[0];
156 assign adc_data[3] = CON_C[11:0];
157*/
158/*
159 adc_para adc_para_unit (
160 .lvds_dco(ADC_DCO),
161 .lvds_fco(ADC_FCO),
162 .para_data_ready(CON_CCLK[0]),
163 .para_data(CON_C[11:0]),
164 .adc_data(adc_data[3]));
165*/
166/*
167 wire adc_pll_clk;
168
169 adc_pll adc_pll_unit(
170 .inclk0(ADC_FCO),
171 .c0(adc_pll_clk));
172*/
173
174 wire tst_adc_clk;
175 wire [11:0] tst_adc_data;
176
177 test test_unit(
178 .clk(CLK_50MHz),
179 .tst_clk(tst_adc_clk),
180 .tst_data(tst_adc_data));
181
182 assign adc_clk[2] = tst_adc_clk;
183 assign adc_data[2] = tst_adc_data;
184
185/*
186 altserial_flash_loader #(
187 .enable_shared_access("OFF"),
188 .enhanced_mode(1),
189 .intended_device_family("Cyclone III")) sfl_unit (
190 .noe(1'b0),
191 .asmi_access_granted(),
192 .asmi_access_request(),
193 .data0out(),
194 .dclkin(),
195 .scein(),
196 .sdoin());
197*/
198/*
199 adc_lvds #(
200 .size(3),
201 .width(12)) adc_lvds_unit (
202 .lvds_dco(ADC_DCO),
203// .lvds_dco(adc_pll_clk),
204 .lvds_fco(ADC_FCO),
205 .lvds_d(ADC_D),
206 .adc_data({ adc_data[0],
207 adc_data[1],
208 adc_data[2] }));
209*/
210 genvar i;
211 generate
212 for (i = 0; i < 3; i = i + 1)
213 begin : MCA_CHAIN
214 adc_fifo adc_fifo_unit (
215 .adc_clk(adc_clk[i]),
216 .adc_data(adc_data[i]),
217 .polarity(adc_pola[i]),
218 .clk(CLK_50MHz),
219 .ready(adc_data_ready[i]),
220 .raw_data(raw_data[i]),
221 .uwt_data({uwt_flag[i], uwt_data[i]}));
222
223 analyser analyser_unit (
224 .clk(CLK_50MHz),
225 .reset(ana_reset[i]),
226 .data_ready(adc_data_ready[i]),
227 .uwt_flag(uwt_flag[i]),
228 .uwt_data(uwt_data[i]),
229 .threshold(12'd10),
230 .peak_ready(ana_peak_ready[i]),
231 .peak(ana_peak[i]));
232
233 histogram histogram_unit (
234 .clk(CLK_50MHz),
235 .reset(hst_reset[i]),
236 .data_ready(adc_data_ready[i]),
237 .data(raw_data[i]),
238// .data(uwt_data[i]),
239 .address(hst_addr[i]),
240 .q(hst_q[i]));
241/*
242 histogram histogram_unit (
243 .clk(CLK_50MHz),
244 .reset(hst_reset[i]),
245 .data_ready(ana_peak_ready[i]),
246 .data(ana_peak[i]),
247 .address(hst_addr[i]),
248 .q(hst_q[i]));
249*/
250 oscilloscope oscilloscope_unit (
251 .clk(CLK_50MHz),
252 .reset(osc_reset[i]),
253 .data_ready(adc_data_ready[i]),
254 .raw_data(raw_data[i]),
255 .uwt_data(uwt_data[i]),
256 .threshold(osc_thrs[i]),
257 .address(osc_addr[i]),
258 .start_address(osc_start_addr[i]),
259 .q(osc_q[i]));
260 end
261 endgenerate
262
263 integer j;
264
265 always @*
266 begin
267 for (j = 0; j < 4; j = j + 1)
268 begin
269 osc_reset[j] = 1'b0;
270 osc_addr[j] = 10'b0;
271 hst_reset[j] = 1'b0;
272 hst_addr[j] = 12'b0;
273 end
274
275 case({mux_type, mux_chan})
276 3'b000, 3'b001, 3'b010, 3'b011:
277 begin
278 osc_reset[mux_chan] = mux_reset;
279 osc_addr[mux_chan] = mux_addr[9:0];
280 mux_max_byte = 2'd1;
281 mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
282 mux_max_addr = 16'd1023;
283 end
284
285 3'b100, 3'b101, 3'b110, 3'b111:
286 begin
287 hst_reset[mux_chan] = mux_reset;
288 hst_addr[mux_chan] = mux_addr[11:0];
289 mux_max_byte = 2'd3;
290 mux_min_addr = 16'd0;
291 mux_max_addr = 16'd4095;
292 end
293 endcase
294 end
295
296 always @*
297 begin
298 case ({mux_type, mux_byte})
299 3'b000: mux_q = osc_q[mux_chan][7:0];
300 3'b001: mux_q = osc_q[mux_chan][15:8];
301
302 3'b100: mux_q = hst_q[mux_chan][7:0];
303 3'b101: mux_q = hst_q[mux_chan][15:8];
304 3'b110: mux_q = hst_q[mux_chan][23:16];
305 3'b111: mux_q = hst_q[mux_chan][31:24];
306
307 default: mux_q = 8'd0;
308 endcase
309 end
310
311 wire i2c_aclr;
312 wire i2c_wrreq;
313 wire i2c_full;
314 wire [15:0] i2c_data;
315
316 i2c_fifo i2c_unit(
317 .clk(CLK_50MHz),
318 .aclr(i2c_aclr),
319 .wrreq(i2c_wrreq),
320 .data(i2c_data),
321 .full(i2c_full),
322/*
323 normal connection
324 .i2c_sda(I2C_SDA),
325 .i2c_scl(I2C_SCL),
326
327 following is a cross wire connection for EPT
328*/
329 .i2c_sda(I2C_SCL),
330 .i2c_scl(I2C_SDA));
331
332 control control_unit (
333 .clk(CLK_50MHz),
334 .rx_empty(usb_rx_empty),
335 .tx_full(usb_tx_full),
336 .rx_data(usb_rx_data),
337 .mux_max_byte(mux_max_byte),
338 .mux_min_addr(mux_min_addr),
339 .mux_max_addr(mux_max_addr),
340 .mux_q(mux_q),
341 .mux_reset(mux_reset),
342 .mux_type(mux_type),
343 .mux_chan(mux_chan),
344 .mux_byte(mux_byte),
345 .mux_addr(mux_addr),
346 .rx_rdreq(usb_rx_rdreq),
347 .tx_wrreq(usb_tx_wrreq),
348 .tx_data(usb_tx_data),
349 .ram_we(RAM_WE),
350 .ram_addr(RAM_ADDR),
351 .ram_data({RAM_DQA, RAM_DQAP, RAM_DQB, RAM_DQBP}),
352 .i2c_wrreq(i2c_wrreq),
353 .i2c_data(i2c_data),
354 .i2c_full(i2c_full),
355 .led(LED));
356
357endmodule
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