source: trunk/MultiChannelUSB/Paella.v@ 57

Last change on this file since 57 was 54, checked in by demin, 15 years ago

adapat memory access to normal memory clock
File size: 9.7 KB
Line 
1module Paella
2 (
3 input wire CLK_50MHz,
4 output wire LED,
5
6 inout wire [3:0] TRG,
7 inout wire [6:0] CON_A,
8 inout wire [15:0] CON_B,
9 inout wire [12:0] CON_C,
10 input wire [1:0] CON_BCLK,
11 input wire [1:0] CON_CCLK,
12
13 input wire ADC_DCO,
14 input wire ADC_FCO,
15 input wire [2:0] ADC_D,
16
17 output wire USB_SLRD,
18 output wire USB_SLWR,
19 input wire USB_IFCLK,
20 input wire USB_FLAGA, // EMPTY flag for EP6
21 input wire USB_FLAGB, // FULL flag for EP8
22 input wire USB_FLAGC,
23 inout wire USB_PA0,
24 inout wire USB_PA1,
25 output wire USB_PA2,
26 inout wire USB_PA3,
27 output wire USB_PA4,
28 output wire USB_PA5,
29 output wire USB_PA6,
30 inout wire USB_PA7,
31 inout wire [7:0] USB_PB,
32
33 output wire RAM_CLK,
34 output wire RAM_CE1,
35 output wire RAM_WE,
36 output wire [19:0] RAM_ADDR,
37 inout wire RAM_DQAP,
38 inout wire [7:0] RAM_DQA,
39 inout wire RAM_DQBP,
40 inout wire [7:0] RAM_DQB
41 );
42
43 // Turn output ports off
44 assign RAM_CLK = 1'b0;
45 assign RAM_CE1 = 1'b0;
46 assign RAM_WE = 1'b0;
47 assign RAM_ADDR = 20'h00000;
48
49 // Turn inout ports to tri-state
50 assign TRG = 4'bz;
51 assign CON_A = 7'bz;
52 assign CON_B = 16'bz;
53 assign CON_C = 13'bz;
54 assign USB_PA0 = 1'bz;
55 assign USB_PA1 = 1'bz;
56 assign USB_PA3 = 1'bz;
57 assign USB_PA7 = 1'bz;
58 assign RAM_DQAP = 1'bz;
59 assign RAM_DQA = 8'bz;
60 assign RAM_DQBP = 1'bz;
61 assign RAM_DQB = 8'bz;
62
63 assign USB_PA2 = ~usb_rden;
64 assign USB_PA4 = usb_addr[0];
65 assign USB_PA5 = usb_addr[1];
66 assign USB_PA6 = ~usb_pktend;
67
68 reg led_reg;
69 assign LED = led_reg;
70
71 wire usb_wrreq, usb_rdreq, usb_rden, usb_pktend;
72 wire usb_fifo_aclr;
73 reg usb_fifo_tx_wrreq;
74 reg usb_fifo_rx_rdreq;
75 wire usb_fifo_tx_full, usb_fifo_rx_empty;
76 reg [7:0] usb_fifo_tx_data;
77 wire [7:0] usb_fifo_rx_data;
78 wire [1:0] usb_addr;
79
80 assign USB_SLRD = ~usb_rdreq;
81 assign USB_SLWR = ~usb_wrreq;
82
83 usb_fifo usb_fifo_unit
84 (
85 .usb_clk(USB_IFCLK),
86 .usb_data(USB_PB),
87 .usb_full(~USB_FLAGB),
88 .usb_empty(~USB_FLAGA),
89 .usb_wrreq(usb_wrreq),
90 .usb_rdreq(usb_rdreq),
91 .usb_rden(usb_rden),
92 .usb_pktend(usb_pktend),
93 .usb_addr(usb_addr),
94
95 .clk(CLK_50MHz),
96 .aclr(usb_fifo_aclr),
97
98 .tx_full(usb_fifo_tx_full),
99 .tx_wrreq((~usb_fifo_tx_full) & usb_fifo_tx_wrreq),
100 .tx_data(usb_fifo_tx_data),
101
102 .rx_empty(usb_fifo_rx_empty),
103 .rx_rdreq((~usb_fifo_rx_empty) & usb_fifo_rx_rdreq),
104 .rx_q(usb_fifo_rx_data)
105 );
106
107 reg [23:0] rx_counter;
108 reg [10:0] tst_counter;
109
110 reg ana_reset [3:0];
111 wire ana_peak_ready [3:0];
112 wire [11:0] ana_peak [3:0];
113
114 reg osc_reset [3:0];
115 wire [9:0] osc_start_addr [3:0];
116 reg [9:0] osc_addr [3:0];
117 wire [15:0] osc_q [3:0];
118 reg [15:0] osc_q_mux;
119
120 reg hst_reset [3:0];
121 reg [11:0] hst_addr [3:0];
122 wire [23:0] hst_q [3:0];
123
124 reg mux_reset, mux_type;
125 reg [1:0] mux_chan, mux_byte, mux_max_byte;
126 reg [15:0] mux_addr, mux_min_addr, mux_max_addr, mux_num_addr;
127 reg [7:0] mux_q;
128
129 reg [3:0] state1, state2;
130 reg adc_fifo_aclr;
131
132 wire adc_clk [3:0];
133
134
135 wire adc_data_ready [3:0];
136 wire [11:0] adc_data [3:0];
137
138 wire [11:0] raw_data [3:0];
139 wire [11:0] uwt_data [3:0];
140 wire [1:0] uwt_flag [3:0];
141
142 assign adc_clk[0] = ADC_FCO;
143 assign adc_clk[1] = ADC_FCO;
144 assign adc_clk[2] = ADC_FCO;
145
146 assign adc_clk[3] = CON_B[0];
147 assign adc_data[3] = CON_B[12:1];
148
149 wire adc_pll_clk;
150
151 wire tst_adc_clk;
152 reg [11:0] tst_adc_data;
153/*
154 assign adc_clk[3] = tst_adc_clk;
155 assign adc_data[3] = tst_adc_data;
156*/
157/*
158 adc_pll adc_pll_unit(
159 .inclk0(ADC_FCO),
160 .c0(adc_pll_clk));
161*/
162
163 pll pll_unit(
164 .inclk0(CLK_50MHz),
165 .c0(tst_adc_clk));
166
167/*
168 altserial_flash_loader #(
169 .enable_shared_access("OFF"),
170 .enhanced_mode(1),
171 .intended_device_family("Cyclone III")) sfl_unit (
172 .noe(1'b0),
173 .asmi_access_granted(),
174 .asmi_access_request(),
175 .data0out(),
176 .dclkin(),
177 .scein(),
178 .sdoin());
179*/
180
181 adc_lvds adc_lvds_unit (
182 .lvds_dco(ADC_DCO),
183// .lvds_dco(adc_pll_clk),
184 .lvds_fco(ADC_FCO),
185 .lvds_d(ADC_D),
186 .adc_db(adc_data[0]),
187 .adc_dc(adc_data[1]),
188 .adc_dd(adc_data[2]));
189
190 genvar i;
191 generate
192 for (i = 0; i < 4; i = i + 1)
193 begin : MCA_CHAIN
194 adc_fifo adc_fifo_unit (
195 .adc_clk(adc_clk[i]),
196 .adc_data(adc_data[i]),
197 .aclr(adc_fifo_aclr),
198 .rdclk(CLK_50MHz),
199 .ready(adc_data_ready[i]),
200 .raw_data(raw_data[i]),
201 .uwt_data({uwt_flag[i], uwt_data[i]}));
202
203 analyser analyser_unit (
204 .clk(CLK_50MHz),
205 .reset(ana_reset[i]),
206 .data_ready(adc_data_ready[i]),
207 .uwt_flag(uwt_flag[i]),
208 .uwt_data(uwt_data[i]),
209 .threshold(12'd10),
210 .peak_ready(ana_peak_ready[i]),
211 .peak(ana_peak[i]));
212
213 histogram histogram_unit (
214 .clk(CLK_50MHz),
215 .reset(hst_reset[i]),
216 .data_ready(adc_data_ready[i]),
217// .data(raw_data[i]),
218 .data(uwt_data[i]),
219 .address(hst_addr[i]),
220 .q(hst_q[i]));
221/*
222 histogram histogram_unit (
223 .clk(CLK_50MHz),
224 .reset(hst_reset[i]),
225 .data_ready(ana_peak_ready[i]),
226 .data(ana_peak[i]),
227 .address(hst_addr[i]),
228 .q(hst_q[i]));
229*/
230 oscilloscope oscilloscope_unit (
231 .clk(CLK_50MHz),
232 .reset(osc_reset[i]),
233 .data_ready(adc_data_ready[i]),
234 .raw_data(raw_data[i]),
235 .uwt_data(uwt_data[i]),
236 .threshold(16'd40),
237 .address(osc_addr[i]),
238 .start_address(osc_start_addr[i]),
239 .q(osc_q[i]));
240 end
241 endgenerate
242
243 integer j;
244
245 always @*
246 begin
247 for (j = 0; j < 4; j = j + 1)
248 begin
249 osc_reset[j] = 1'b0;
250 osc_addr[j] = 10'b0;
251 hst_reset[j] = 1'b0;
252 hst_addr[j] = 12'b0;
253 end
254
255 case({mux_type,mux_chan})
256 3'b000, 3'b001, 3'b010, 3'b011:
257 begin
258 osc_reset[mux_chan] = mux_reset;
259 osc_addr[mux_chan] = mux_addr[9:0];
260 mux_max_byte = 2'd1;
261 mux_min_addr = {6'd0, osc_start_addr[mux_chan]};
262 mux_num_addr = 16'd1023;
263 end
264
265 3'b100, 3'b101, 3'b110, 3'b111:
266 begin
267 hst_reset[mux_chan] = mux_reset;
268 hst_addr[mux_chan] = mux_addr[11:0];
269 mux_max_byte = 2'd2;
270 mux_min_addr = 16'd0;
271 mux_num_addr = 16'd4095;
272 end
273 endcase
274 end
275
276 always @*
277 begin
278 case ({mux_type,mux_byte})
279 5'b000: mux_q = osc_q[mux_chan][7:0];
280 5'b001: mux_q = osc_q[mux_chan][15:8];
281
282 5'b100: mux_q = hst_q[mux_chan][7:0];
283 5'b101: mux_q = hst_q[mux_chan][15:8];
284 5'b110: mux_q = hst_q[mux_chan][23:16];
285
286 default: mux_q = 8'd0;
287 endcase
288 end
289
290
291 always @(posedge CLK_50MHz)
292 begin
293 if (~usb_fifo_rx_empty)
294 begin
295 led_reg <= 1'b0;
296 rx_counter <= 24'd0;
297 end
298 else
299 begin
300 if (&rx_counter)
301 begin
302 led_reg <= 1'b1;
303 end
304 else
305 begin
306 rx_counter <= rx_counter + 24'd1;
307 end
308 end
309
310 case(state1)
311 1:
312 begin
313 usb_fifo_rx_rdreq <= 1'b1;
314 usb_fifo_tx_wrreq <= 1'b0;
315 mux_type <= 1'b0;
316 mux_chan <= 2'd0;
317 mux_byte <= 2'd0;
318 mux_reset <= 1'b0;
319 state1 <= 4'd2;
320 end
321
322 2:
323 begin
324 if (~usb_fifo_rx_empty)
325 begin
326 case (usb_fifo_rx_data)
327 8'h40, 8'h41, 8'h42, 8'h43, 8'h50, 8'h51, 8'h52, 8'h53:
328 begin
329 usb_fifo_rx_rdreq <= 1'b0;
330 mux_type <= usb_fifo_rx_data[4];
331 mux_chan <= usb_fifo_rx_data[1:0];
332 mux_reset <= 1'b1;
333 state1 <= 4'd1;
334 end
335
336 8'h60, 8'h61, 8'h62, 8'h63, 8'h70, 8'h71, 8'h72, 8'h73:
337 begin
338 usb_fifo_rx_rdreq <= 1'b0;
339 mux_type <= usb_fifo_rx_data[4];
340 mux_chan <= usb_fifo_rx_data[1:0];
341 state1 <= 4'd3;
342 end
343
344 8'h30:
345 begin
346 usb_fifo_rx_rdreq <= 1'b0;
347 state1 <= 4'd1;
348 end
349
350 8'h31:
351 begin
352 usb_fifo_rx_rdreq <= 1'b0;
353 tst_counter <= 11'd0;
354 state1 <= 4'd6;
355 end
356 endcase
357 end
358 end
359 // mux transfer
360 3:
361 begin
362 mux_addr <= mux_min_addr;
363 mux_max_addr <= mux_min_addr + mux_num_addr;
364 mux_byte <= 2'd0;
365 state1 <= 4'd4;
366 end
367
368 4:
369 begin
370 usb_fifo_tx_wrreq <= 1'b0;
371 state1 <= 4'd5;
372 end
373
374 5:
375 begin
376 if (~usb_fifo_tx_full)
377 begin
378 usb_fifo_tx_data <= mux_q;
379 usb_fifo_tx_wrreq <= 1'b1;
380 if ((mux_byte == mux_max_byte) && (mux_addr == mux_max_addr))
381 begin
382 state1 <= 4'd1;
383 end
384 else
385 begin
386 state1 <= 4'd4;
387 if (mux_byte == mux_max_byte)
388 begin
389 mux_addr <= mux_addr + 16'd1;
390 mux_byte <= 2'd0;
391 end
392 else
393 begin
394 mux_byte <= mux_byte + 2'd1;
395 end
396 end
397 end
398 end
399
400 // tst transfer
401 6:
402 begin
403 usb_fifo_tx_data <= tst_counter;
404 usb_fifo_tx_wrreq <= 1'b1;
405 tst_counter <= tst_counter + 11'd1;
406 state1 <= 4'd8;
407 end
408 7:
409 begin
410 if (~usb_fifo_tx_full)
411 begin
412 usb_fifo_tx_data <= tst_counter;
413 if (tst_counter == 11'd0)
414 begin
415 state1 <= 4'd9;
416 end
417 else
418 begin
419 tst_counter <= tst_counter + 11'd1;
420 end
421 end
422 end
423 8:
424 begin
425 if (~usb_fifo_tx_full)
426 begin
427 usb_fifo_tx_wrreq <= 1'b0;
428 state1 <= 4'd1;
429 end
430 end
431
432 default:
433 begin
434 state1 <= 4'd1;
435 end
436 endcase
437 end
438
439 always @ (posedge tst_adc_clk)
440 begin
441 case (state2)
442 1:
443 begin
444 tst_adc_data <= 12'd0;
445 state2 <= 4'd2;
446 end
447
448 2:
449 begin
450 tst_adc_data <= 12'd1024;
451 state2 <= 4'd3;
452 end
453
454 3:
455 begin
456 tst_adc_data <= 12'd2048;
457 state2 <= 4'd4;
458 end
459
460 4:
461 begin
462 tst_adc_data <= 12'd3072;
463 state2 <= 4'd5;
464 end
465
466 5:
467 begin
468 tst_adc_data <= 12'd4095;
469 state2 <= 4'd1;
470 end
471
472 default:
473 begin
474 state2 <= 4'd1;
475 end
476 endcase
477 end
478
479endmodule
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