source: trunk/MultiChannelCOM/ram4096x32.v@ 51

Last change on this file since 51 was 2, checked in by demin, 15 years ago

first working version
File size: 10.5 KB
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[2]1// megafunction wizard: %RAM: 2-PORT%
2// GENERATION: STANDARD
3// VERSION: WM1.0
4// MODULE: altsyncram
5
6// ============================================================
7// File Name: ram4096x32.v
8// Megafunction Name(s):
9// altsyncram
10//
11// Simulation Library Files(s):
12// altera_mf
13// ============================================================
14// ************************************************************
15// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16//
17// 9.0 Build 132 02/25/2009 SJ Web Edition
18// ************************************************************
19
20
21//Copyright (C) 1991-2009 Altera Corporation
22//Your use of Altera Corporation's design tools, logic functions
23//and other software and tools, and its AMPP partner logic
24//functions, and any output files from any of the foregoing
25//(including device programming or simulation files), and any
26//associated documentation or information are expressly subject
27//to the terms and conditions of the Altera Program License
28//Subscription Agreement, Altera MegaCore Function License
29//Agreement, or other applicable license agreement, including,
30//without limitation, that your use is for the sole purpose of
31//programming logic devices manufactured by Altera and sold by
32//Altera or its authorized distributors. Please refer to the
33//applicable agreement for further details.
34
35
36// synopsys translate_off
37`timescale 1 ps / 1 ps
38// synopsys translate_on
39module ram4096x32 (
40 address_a,
41 address_b,
42 clock,
43 data_a,
44 data_b,
45 wren_a,
46 wren_b,
47 q_a,
48 q_b);
49
50 input [11:0] address_a;
51 input [11:0] address_b;
52 input clock;
53 input [31:0] data_a;
54 input [31:0] data_b;
55 input wren_a;
56 input wren_b;
57 output [31:0] q_a;
58 output [31:0] q_b;
59`ifndef ALTERA_RESERVED_QIS
60// synopsys translate_off
61`endif
62 tri1 wren_a;
63 tri1 wren_b;
64`ifndef ALTERA_RESERVED_QIS
65// synopsys translate_on
66`endif
67
68 wire [31:0] sub_wire0;
69 wire [31:0] sub_wire1;
70 wire [31:0] q_a = sub_wire0[31:0];
71 wire [31:0] q_b = sub_wire1[31:0];
72
73 altsyncram altsyncram_component (
74 .wren_a (wren_a),
75 .clock0 (clock),
76 .wren_b (wren_b),
77 .address_a (address_a),
78 .address_b (address_b),
79 .data_a (data_a),
80 .data_b (data_b),
81 .q_a (sub_wire0),
82 .q_b (sub_wire1),
83 .aclr0 (1'b0),
84 .aclr1 (1'b0),
85 .addressstall_a (1'b0),
86 .addressstall_b (1'b0),
87 .byteena_a (1'b1),
88 .byteena_b (1'b1),
89 .clock1 (1'b1),
90 .clocken0 (1'b1),
91 .clocken1 (1'b1),
92 .clocken2 (1'b1),
93 .clocken3 (1'b1),
94 .eccstatus (),
95 .rden_a (1'b1),
96 .rden_b (1'b1));
97 defparam
98 altsyncram_component.address_reg_b = "CLOCK0",
99 altsyncram_component.clock_enable_input_a = "BYPASS",
100 altsyncram_component.clock_enable_input_b = "BYPASS",
101 altsyncram_component.clock_enable_output_a = "BYPASS",
102 altsyncram_component.clock_enable_output_b = "BYPASS",
103 altsyncram_component.indata_reg_b = "CLOCK0",
104 altsyncram_component.intended_device_family = "Cyclone II",
105 altsyncram_component.lpm_type = "altsyncram",
106 altsyncram_component.numwords_a = 4096,
107 altsyncram_component.numwords_b = 4096,
108 altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
109 altsyncram_component.outdata_aclr_a = "NONE",
110 altsyncram_component.outdata_aclr_b = "NONE",
111 altsyncram_component.outdata_reg_a = "UNREGISTERED",
112 altsyncram_component.outdata_reg_b = "UNREGISTERED",
113 altsyncram_component.power_up_uninitialized = "FALSE",
114 altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
115 altsyncram_component.widthad_a = 12,
116 altsyncram_component.widthad_b = 12,
117 altsyncram_component.width_a = 32,
118 altsyncram_component.width_b = 32,
119 altsyncram_component.width_byteena_a = 1,
120 altsyncram_component.width_byteena_b = 1,
121 altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
122
123
124endmodule
125
126// ============================================================
127// CNX file retrieval info
128// ============================================================
129// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
130// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
131// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
132// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
133// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
134// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
135// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
136// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
137// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
138// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
139// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
140// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
141// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
142// Retrieval info: PRIVATE: CLRq NUMERIC "0"
143// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
144// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
145// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
146// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
147// Retrieval info: PRIVATE: Clock NUMERIC "0"
148// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
149// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
150// Retrieval info: PRIVATE: ECC NUMERIC "0"
151// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
152// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
153// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
154// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
155// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
156// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
157// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
158// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
159// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
160// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
161// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
162// Retrieval info: PRIVATE: MIFfilename STRING ""
163// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
164// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
165// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
166// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
167// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
168// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
169// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
170// Retrieval info: PRIVATE: REGdata NUMERIC "1"
171// Retrieval info: PRIVATE: REGq NUMERIC "0"
172// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
173// Retrieval info: PRIVATE: REGrren NUMERIC "0"
174// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
175// Retrieval info: PRIVATE: REGwren NUMERIC "1"
176// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
177// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
178// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
179// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
180// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
181// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
182// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
183// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
184// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
185// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
186// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
187// Retrieval info: PRIVATE: enable NUMERIC "0"
188// Retrieval info: PRIVATE: rden NUMERIC "0"
189// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
190// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
191// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
192// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
193// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
194// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
195// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
196// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
197// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
198// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
199// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
200// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
201// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
202// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
203// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
204// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
205// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
206// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
207// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
208// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
209// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
210// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
211// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
212// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
213// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL address_a[11..0]
214// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL address_b[11..0]
215// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
216// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL data_a[31..0]
217// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL data_b[31..0]
218// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL q_a[31..0]
219// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL q_b[31..0]
220// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
221// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
222// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
223// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
224// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
225// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
226// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
227// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
228// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
229// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
230// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
231// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
232// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32.v TRUE
233// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32.inc FALSE
234// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32.cmp TRUE
235// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32.bsf FALSE
236// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32_inst.v FALSE
237// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32_bb.v TRUE
238// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32_waveforms.html TRUE
239// Retrieval info: GEN_FILE: TYPE_NORMAL ram4096x32_wave*.jpg FALSE
240// Retrieval info: LIB_FILE: altera_mf
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