[2] | 1 | // megafunction wizard: %RAM: 2-PORT%
|
---|
| 2 | // GENERATION: STANDARD
|
---|
| 3 | // VERSION: WM1.0
|
---|
| 4 | // MODULE: altsyncram
|
---|
| 5 |
|
---|
| 6 | // ============================================================
|
---|
| 7 | // File Name: ram1024x16.v
|
---|
| 8 | // Megafunction Name(s):
|
---|
| 9 | // altsyncram
|
---|
| 10 | //
|
---|
| 11 | // Simulation Library Files(s):
|
---|
| 12 | // altera_mf
|
---|
| 13 | // ============================================================
|
---|
| 14 | // ************************************************************
|
---|
| 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
---|
| 16 | //
|
---|
| 17 | // 9.0 Build 132 02/25/2009 SJ Web Edition
|
---|
| 18 | // ************************************************************
|
---|
| 19 |
|
---|
| 20 |
|
---|
| 21 | //Copyright (C) 1991-2009 Altera Corporation
|
---|
| 22 | //Your use of Altera Corporation's design tools, logic functions
|
---|
| 23 | //and other software and tools, and its AMPP partner logic
|
---|
| 24 | //functions, and any output files from any of the foregoing
|
---|
| 25 | //(including device programming or simulation files), and any
|
---|
| 26 | //associated documentation or information are expressly subject
|
---|
| 27 | //to the terms and conditions of the Altera Program License
|
---|
| 28 | //Subscription Agreement, Altera MegaCore Function License
|
---|
| 29 | //Agreement, or other applicable license agreement, including,
|
---|
| 30 | //without limitation, that your use is for the sole purpose of
|
---|
| 31 | //programming logic devices manufactured by Altera and sold by
|
---|
| 32 | //Altera or its authorized distributors. Please refer to the
|
---|
| 33 | //applicable agreement for further details.
|
---|
| 34 |
|
---|
| 35 |
|
---|
| 36 | // synopsys translate_off
|
---|
| 37 | `timescale 1 ps / 1 ps
|
---|
| 38 | // synopsys translate_on
|
---|
| 39 | module ram1024x16 (
|
---|
| 40 | clock,
|
---|
| 41 | data,
|
---|
| 42 | rdaddress,
|
---|
| 43 | wraddress,
|
---|
| 44 | wren,
|
---|
| 45 | q);
|
---|
| 46 |
|
---|
| 47 | input clock;
|
---|
| 48 | input [15:0] data;
|
---|
| 49 | input [9:0] rdaddress;
|
---|
| 50 | input [9:0] wraddress;
|
---|
| 51 | input wren;
|
---|
| 52 | output [15:0] q;
|
---|
| 53 | `ifndef ALTERA_RESERVED_QIS
|
---|
| 54 | // synopsys translate_off
|
---|
| 55 | `endif
|
---|
| 56 | tri1 wren;
|
---|
| 57 | `ifndef ALTERA_RESERVED_QIS
|
---|
| 58 | // synopsys translate_on
|
---|
| 59 | `endif
|
---|
| 60 |
|
---|
| 61 | wire [15:0] sub_wire0;
|
---|
| 62 | wire [15:0] q = sub_wire0[15:0];
|
---|
| 63 |
|
---|
| 64 | altsyncram altsyncram_component (
|
---|
| 65 | .wren_a (wren),
|
---|
| 66 | .clock0 (clock),
|
---|
| 67 | .address_a (wraddress),
|
---|
| 68 | .address_b (rdaddress),
|
---|
| 69 | .data_a (data),
|
---|
| 70 | .q_b (sub_wire0),
|
---|
| 71 | .aclr0 (1'b0),
|
---|
| 72 | .aclr1 (1'b0),
|
---|
| 73 | .addressstall_a (1'b0),
|
---|
| 74 | .addressstall_b (1'b0),
|
---|
| 75 | .byteena_a (1'b1),
|
---|
| 76 | .byteena_b (1'b1),
|
---|
| 77 | .clock1 (1'b1),
|
---|
| 78 | .clocken0 (1'b1),
|
---|
| 79 | .clocken1 (1'b1),
|
---|
| 80 | .clocken2 (1'b1),
|
---|
| 81 | .clocken3 (1'b1),
|
---|
| 82 | .data_b ({16{1'b1}}),
|
---|
| 83 | .eccstatus (),
|
---|
| 84 | .q_a (),
|
---|
| 85 | .rden_a (1'b1),
|
---|
| 86 | .rden_b (1'b1),
|
---|
| 87 | .wren_b (1'b0));
|
---|
| 88 | defparam
|
---|
| 89 | altsyncram_component.address_reg_b = "CLOCK0",
|
---|
| 90 | altsyncram_component.clock_enable_input_a = "BYPASS",
|
---|
| 91 | altsyncram_component.clock_enable_input_b = "BYPASS",
|
---|
| 92 | altsyncram_component.clock_enable_output_a = "BYPASS",
|
---|
| 93 | altsyncram_component.clock_enable_output_b = "BYPASS",
|
---|
| 94 | altsyncram_component.intended_device_family = "Cyclone II",
|
---|
| 95 | altsyncram_component.lpm_type = "altsyncram",
|
---|
| 96 | altsyncram_component.numwords_a = 1024,
|
---|
| 97 | altsyncram_component.numwords_b = 1024,
|
---|
| 98 | altsyncram_component.operation_mode = "DUAL_PORT",
|
---|
| 99 | altsyncram_component.outdata_aclr_b = "NONE",
|
---|
| 100 | altsyncram_component.outdata_reg_b = "UNREGISTERED",
|
---|
| 101 | altsyncram_component.power_up_uninitialized = "FALSE",
|
---|
| 102 | altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
|
---|
| 103 | altsyncram_component.widthad_a = 10,
|
---|
| 104 | altsyncram_component.widthad_b = 10,
|
---|
| 105 | altsyncram_component.width_a = 16,
|
---|
| 106 | altsyncram_component.width_b = 16,
|
---|
| 107 | altsyncram_component.width_byteena_a = 1;
|
---|
| 108 |
|
---|
| 109 |
|
---|
| 110 | endmodule
|
---|
| 111 |
|
---|
| 112 | // ============================================================
|
---|
| 113 | // CNX file retrieval info
|
---|
| 114 | // ============================================================
|
---|
| 115 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
---|
| 116 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
|
---|
| 117 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
|
---|
| 118 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
|
---|
| 119 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
|
---|
| 120 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
|
---|
| 121 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
---|
| 122 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
---|
| 123 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
---|
| 124 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
|
---|
| 125 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
---|
| 126 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
|
---|
| 127 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
---|
| 128 | // Retrieval info: PRIVATE: CLRq NUMERIC "0"
|
---|
| 129 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
|
---|
| 130 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
---|
| 131 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
---|
| 132 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
---|
| 133 | // Retrieval info: PRIVATE: Clock NUMERIC "0"
|
---|
| 134 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
---|
| 135 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
---|
| 136 | // Retrieval info: PRIVATE: ECC NUMERIC "0"
|
---|
| 137 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
---|
| 138 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
---|
| 139 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
|
---|
| 140 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
|
---|
| 141 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
---|
| 142 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
---|
| 143 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
---|
| 144 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
---|
| 145 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
---|
| 146 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
|
---|
| 147 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
---|
| 148 | // Retrieval info: PRIVATE: MIFfilename STRING ""
|
---|
| 149 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
|
---|
| 150 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
---|
| 151 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
|
---|
| 152 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
---|
| 153 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
|
---|
| 154 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
---|
| 155 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
|
---|
| 156 | // Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
---|
| 157 | // Retrieval info: PRIVATE: REGq NUMERIC "1"
|
---|
| 158 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
|
---|
| 159 | // Retrieval info: PRIVATE: REGrren NUMERIC "1"
|
---|
| 160 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
---|
| 161 | // Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
---|
| 162 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
---|
| 163 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
|
---|
| 164 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
|
---|
| 165 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0"
|
---|
| 166 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
|
---|
| 167 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
|
---|
| 168 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
|
---|
| 169 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
|
---|
| 170 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
---|
| 171 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
|
---|
| 172 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
---|
| 173 | // Retrieval info: PRIVATE: enable NUMERIC "0"
|
---|
| 174 | // Retrieval info: PRIVATE: rden NUMERIC "0"
|
---|
| 175 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
|
---|
| 176 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
---|
| 177 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
---|
| 178 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
---|
| 179 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
---|
| 180 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
---|
| 181 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
---|
| 182 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
|
---|
| 183 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
|
---|
| 184 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
|
---|
| 185 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
---|
| 186 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
|
---|
| 187 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
---|
| 188 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
|
---|
| 189 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
|
---|
| 190 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
|
---|
| 191 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
|
---|
| 192 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
|
---|
| 193 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
|
---|
| 194 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
---|
| 195 | // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
|
---|
| 196 | // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
|
---|
| 197 | // Retrieval info: USED_PORT: rdaddress 0 0 10 0 INPUT NODEFVAL rdaddress[9..0]
|
---|
| 198 | // Retrieval info: USED_PORT: wraddress 0 0 10 0 INPUT NODEFVAL wraddress[9..0]
|
---|
| 199 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
|
---|
| 200 | // Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
|
---|
| 201 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
---|
| 202 | // Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0
|
---|
| 203 | // Retrieval info: CONNECT: @address_a 0 0 10 0 wraddress 0 0 10 0
|
---|
| 204 | // Retrieval info: CONNECT: @address_b 0 0 10 0 rdaddress 0 0 10 0
|
---|
| 205 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
---|
| 206 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
---|
| 207 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16.v TRUE
|
---|
| 208 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16.inc FALSE
|
---|
| 209 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16.cmp TRUE
|
---|
| 210 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16.bsf FALSE
|
---|
| 211 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16_inst.v FALSE
|
---|
| 212 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16_bb.v TRUE
|
---|
| 213 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16_waveforms.html TRUE
|
---|
| 214 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram1024x16_wave*.jpg FALSE
|
---|
| 215 | // Retrieval info: LIB_FILE: altera_mf
|
---|