1 | // megafunction wizard: %FIFO%
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2 | // GENERATION: STANDARD
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3 | // VERSION: WM1.0
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4 | // MODULE: dcfifo
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5 |
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6 | // ============================================================
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7 | // File Name: fifo32x14.v
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8 | // Megafunction Name(s):
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9 | // dcfifo
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10 | //
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11 | // Simulation Library Files(s):
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12 | // altera_mf
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13 | // ============================================================
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14 | // ************************************************************
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15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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16 | //
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17 | // 9.0 Build 132 02/25/2009 SJ Web Edition
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18 | // ************************************************************
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19 |
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20 |
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21 | //Copyright (C) 1991-2009 Altera Corporation
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22 | //Your use of Altera Corporation's design tools, logic functions
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23 | //and other software and tools, and its AMPP partner logic
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24 | //functions, and any output files from any of the foregoing
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25 | //(including device programming or simulation files), and any
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26 | //associated documentation or information are expressly subject
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27 | //to the terms and conditions of the Altera Program License
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28 | //Subscription Agreement, Altera MegaCore Function License
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29 | //Agreement, or other applicable license agreement, including,
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30 | //without limitation, that your use is for the sole purpose of
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31 | //programming logic devices manufactured by Altera and sold by
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32 | //Altera or its authorized distributors. Please refer to the
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33 | //applicable agreement for further details.
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34 |
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35 |
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36 | // synopsys translate_off
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37 | `timescale 1 ps / 1 ps
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38 | // synopsys translate_on
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39 | module fifo32x14 (
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40 | aclr,
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41 | data,
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42 | rdclk,
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43 | rdreq,
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44 | wrclk,
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45 | wrreq,
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46 | q,
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47 | rdempty,
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48 | wrfull);
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49 |
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50 | input aclr;
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51 | input [13:0] data;
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52 | input rdclk;
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53 | input rdreq;
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54 | input wrclk;
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55 | input wrreq;
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56 | output [13:0] q;
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57 | output rdempty;
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58 | output wrfull;
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59 | `ifndef ALTERA_RESERVED_QIS
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60 | // synopsys translate_off
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61 | `endif
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62 | tri0 aclr;
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63 | `ifndef ALTERA_RESERVED_QIS
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64 | // synopsys translate_on
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65 | `endif
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66 |
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67 | wire sub_wire0;
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68 | wire sub_wire1;
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69 | wire [13:0] sub_wire2;
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70 | wire rdempty = sub_wire0;
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71 | wire wrfull = sub_wire1;
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72 | wire [13:0] q = sub_wire2[13:0];
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73 |
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74 | dcfifo dcfifo_component (
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75 | .wrclk (wrclk),
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76 | .rdreq (rdreq),
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77 | .aclr (aclr),
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78 | .rdclk (rdclk),
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79 | .wrreq (wrreq),
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80 | .data (data),
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81 | .rdempty (sub_wire0),
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82 | .wrfull (sub_wire1),
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83 | .q (sub_wire2)
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84 | // synopsys translate_off
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85 | ,
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86 | .rdfull (),
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87 | .rdusedw (),
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88 | .wrempty (),
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89 | .wrusedw ()
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90 | // synopsys translate_on
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91 | );
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92 | defparam
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93 | dcfifo_component.intended_device_family = "Cyclone II",
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94 | dcfifo_component.lpm_numwords = 32,
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95 | dcfifo_component.lpm_showahead = "ON",
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96 | dcfifo_component.lpm_type = "dcfifo",
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97 | dcfifo_component.lpm_width = 14,
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98 | dcfifo_component.lpm_widthu = 5,
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99 | dcfifo_component.overflow_checking = "ON",
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100 | dcfifo_component.rdsync_delaypipe = 4,
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101 | dcfifo_component.underflow_checking = "ON",
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102 | dcfifo_component.use_eab = "ON",
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103 | dcfifo_component.write_aclr_synch = "OFF",
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104 | dcfifo_component.wrsync_delaypipe = 4;
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105 |
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106 |
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107 | endmodule
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108 |
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109 | // ============================================================
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110 | // CNX file retrieval info
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111 | // ============================================================
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112 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
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113 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
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114 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
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115 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
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116 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
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117 | // Retrieval info: PRIVATE: Clock NUMERIC "4"
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118 | // Retrieval info: PRIVATE: Depth NUMERIC "32"
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119 | // Retrieval info: PRIVATE: Empty NUMERIC "1"
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120 | // Retrieval info: PRIVATE: Full NUMERIC "1"
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121 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
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122 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
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123 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
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124 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
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125 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
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126 | // Retrieval info: PRIVATE: Optimize NUMERIC "0"
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127 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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128 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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129 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
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130 | // Retrieval info: PRIVATE: UsedW NUMERIC "1"
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131 | // Retrieval info: PRIVATE: Width NUMERIC "14"
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132 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
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133 | // Retrieval info: PRIVATE: diff_widths NUMERIC "0"
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134 | // Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
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135 | // Retrieval info: PRIVATE: output_width NUMERIC "14"
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136 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
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137 | // Retrieval info: PRIVATE: rsFull NUMERIC "0"
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138 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
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139 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
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140 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
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141 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
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142 | // Retrieval info: PRIVATE: wsFull NUMERIC "1"
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143 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
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144 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
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145 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
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146 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
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147 | // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
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148 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "14"
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149 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
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150 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
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151 | // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
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152 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
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153 | // Retrieval info: CONSTANT: USE_EAB STRING "ON"
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154 | // Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
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155 | // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
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156 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
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157 | // Retrieval info: USED_PORT: data 0 0 14 0 INPUT NODEFVAL data[13..0]
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158 | // Retrieval info: USED_PORT: q 0 0 14 0 OUTPUT NODEFVAL q[13..0]
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159 | // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
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160 | // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
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161 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
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162 | // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
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163 | // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
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164 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
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165 | // Retrieval info: CONNECT: @data 0 0 14 0 data 0 0 14 0
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166 | // Retrieval info: CONNECT: q 0 0 14 0 @q 0 0 14 0
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167 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
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168 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
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169 | // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
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170 | // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
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171 | // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
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172 | // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
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173 | // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
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174 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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175 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14.v TRUE
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176 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14.inc FALSE
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177 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14.cmp TRUE
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178 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14.bsf FALSE
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179 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14_inst.v FALSE
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180 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14_bb.v TRUE
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181 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14_waveforms.html TRUE
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182 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo32x14_wave*.jpg FALSE
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183 | // Retrieval info: LIB_FILE: altera_mf
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