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| [2] | 1 | module baud_gen
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| 2 | #(
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| 3 | parameter INC=1208, // counter increment (115200*16*32768/F_clk)
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| 4 | DIV=1 // divider (baud rate = 115200/D)
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| 5 | )
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| 6 | (
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| 7 | input wire clk, reset,
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| 8 | output wire max_tick
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| 9 | );
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| 10 |
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| 11 | //signal declaration
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| 12 | reg [15:0] acc_reg;
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| 13 | reg [7:0] div_reg;
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| 14 |
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| 15 | wire div_reg_max = (div_reg == (DIV-1));
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| 16 |
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| 17 | // body
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| 18 | always @(posedge clk, posedge reset)
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| 19 | begin
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| 20 | if (reset)
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| 21 | begin
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| 22 | acc_reg <= 0;
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| 23 | div_reg <= 0;
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| 24 | end
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| 25 | else
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| 26 | begin
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| 27 | acc_reg <= acc_reg[14:0] + INC;
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| 28 | if (acc_reg[15])
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| 29 | div_reg <= div_reg_max ? 0 : div_reg + 16'd1;
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| 30 | end
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| 31 | end
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| 32 |
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| 33 | // output logic
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| 34 | assign max_tick = acc_reg[15] & div_reg_max;
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| 35 |
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| 36 | endmodule
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