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[2] | 1 | module adc_fifo
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| 2 | (
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| 3 | input wire adc_dr,
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| 4 | input wire adc_or,
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| 5 | input wire [11:0] adc_data,
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| 6 |
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| 7 | input wire aclr,
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| 8 | input wire rdclk,
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| 9 | input wire rdreq,
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| 10 | output wire rdempty,
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| 11 | output wire [11:0] raw_data,
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| 12 | output wire [13:0] uwt_data
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| 13 | );
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| 14 |
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| 15 | wire [31:0] uwt_d1, uwt_a1, uwt_peak1;
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| 16 | wire [31:0] uwt_d2, uwt_a2, uwt_peak2;
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| 17 | wire [31:0] uwt_d3, uwt_a3, uwt_peak3;
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| 18 | wire [1:0] uwt_flag1, uwt_flag2, uwt_flag3;
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| 19 |
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| 20 | wire [1:0] wrfull;
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| 21 |
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| 22 | uwt_bior31 #(.L(1)) uwt_1_unit (
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| 23 | .clk(adc_dr),
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| 24 | .x(adc_data),
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| 25 | .d(uwt_d1),
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| 26 | .a(uwt_a1),
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| 27 | .peak(uwt_peak1),
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| 28 | .flag(uwt_flag1));
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| 29 |
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| 30 | uwt_bior31 #(.L(2)) uwt_2_unit (
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| 31 | .clk(adc_dr),
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| 32 | .x(uwt_a1),
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| 33 | .d(uwt_d2),
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| 34 | .a(uwt_a2),
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| 35 | .peak(uwt_peak2),
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| 36 | .flag(uwt_flag2));
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| 37 |
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| 38 | uwt_bior31 #(.L(3)) uwt_3_unit (
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| 39 | .clk(adc_dr),
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| 40 | .x(uwt_a2),
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| 41 | .d(uwt_d3),
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| 42 | .a(uwt_a3),
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| 43 | .peak(uwt_peak3),
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| 44 | .flag(uwt_flag3));
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| 45 |
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| 46 |
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| 47 | fifo32x12 fifo0 (
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| 48 | .aclr(aclr),
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| 49 | .data(adc_data),
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| 50 | .rdclk(rdclk),
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| 51 | .rdreq(rdreq),
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| 52 | .wrclk(adc_dr),
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| 53 | .wrreq(~wrfull[0]),
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| 54 | .q(raw_data),
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| 55 | .rdempty(rdempty),
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| 56 | .wrfull(wrfull[0]));
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| 57 |
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| 58 | fifo32x14 fifo1 (
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| 59 | .aclr(aclr),
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| 60 | .data({uwt_flag3, uwt_peak3[11:0]}),
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| 61 | .rdclk(rdclk),
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| 62 | .rdreq(rdreq),
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| 63 | .wrclk(adc_dr),
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| 64 | .wrreq(~wrfull[1]),
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| 65 | .q(uwt_data),
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| 66 | .rdempty(),
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| 67 | .wrfull(wrfull[1]));
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| 68 |
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| 69 | endmodule
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