source: trunk/MultiChannelCOM/CII_Starter_TOP.v@ 58

Last change on this file since 58 was 2, checked in by demin, 15 years ago

first working version
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1//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
2//use of Altera Corporation's design tools, logic functions and other
3//software and tools, and its AMPP partner logic functions, and any
4//output files any of the foregoing (including device programming or
5//simulation files), and any associated documentation or information are
6//expressly subject to the terms and conditions of the Altera Program
7//License Subscription Agreement or other applicable license agreement,
8//including, without limitation, that your use is for the sole purpose
9//of programming logic devices manufactured by Altera and sold by Altera
10//or its authorized distributors. Please refer to the applicable
11//agreement for further details.
12
13
14module CII_Starter_TOP
15 (
16 //////////////////// Clock Input ////////////////////
17 CLOCK_24, // 24 MHz
18 CLOCK_27, // 27 MHz
19 CLOCK_50, // 50 MHz
20 EXT_CLOCK, // External Clock
21 //////////////////// Push Button ////////////////////
22 KEY, // Pushbutton[3:0]
23 //////////////////// DPDT Switch ////////////////////
24 SW, // Toggle Switch[9:0]
25 //////////////////// 7-SEG Dispaly ////////////////////
26 HEX0, // Seven Segment Digit 0
27 HEX1, // Seven Segment Digit 1
28 HEX2, // Seven Segment Digit 2
29 HEX3, // Seven Segment Digit 3
30 //////////////////////// LED ////////////////////////
31 LEDG, // LED Green[7:0]
32 LEDR, // LED Red[9:0]
33 //////////////////////// UART ////////////////////////
34 UART_TXD, // UART Transmitter
35 UART_RXD, // UART Receiver
36 ///////////////////// SDRAM Interface ////////////////
37 DRAM_DQ, // SDRAM Data bus 16 Bits
38 DRAM_ADDR, // SDRAM Address bus 12 Bits
39 DRAM_LDQM, // SDRAM Low-byte Data Mask
40 DRAM_UDQM, // SDRAM High-byte Data Mask
41 DRAM_WE_N, // SDRAM Write Enable
42 DRAM_CAS_N, // SDRAM Column Address Strobe
43 DRAM_RAS_N, // SDRAM Row Address Strobe
44 DRAM_CS_N, // SDRAM Chip Select
45 DRAM_BA_0, // SDRAM Bank Address 0
46 DRAM_BA_1, // SDRAM Bank Address 0
47 DRAM_CLK, // SDRAM Clock
48 DRAM_CKE, // SDRAM Clock Enable
49 //////////////////// Flash Interface ////////////////
50 FL_DQ, // FLASH Data bus 8 Bits
51 FL_ADDR, // FLASH Address bus 22 Bits
52 FL_WE_N, // FLASH Write Enable
53 FL_RST_N, // FLASH Reset
54 FL_OE_N, // FLASH Output Enable
55 FL_CE_N, // FLASH Chip Enable
56 //////////////////// SRAM Interface ////////////////
57 SRAM_DQ, // SRAM Data bus 16 Bits
58 SRAM_ADDR, // SRAM Address bus 18 Bits
59 SRAM_UB_N, // SRAM High-byte Data Mask
60 SRAM_LB_N, // SRAM Low-byte Data Mask
61 SRAM_WE_N, // SRAM Write Enable
62 SRAM_CE_N, // SRAM Chip Enable
63 SRAM_OE_N, // SRAM Output Enable
64 //////////////////// SD_Card Interface ////////////////
65 SD_DAT, // SD Card Data
66 SD_DAT3, // SD Card Data 3
67 SD_CMD, // SD Card Command Signal
68 SD_CLK, // SD Card Clock
69 //////////////////// USB JTAG link ////////////////////
70 TDI, // CPLD -> FPGA (data in)
71 TCK, // CPLD -> FPGA (clk)
72 TCS, // CPLD -> FPGA (CS)
73 TDO, // FPGA -> CPLD (data out)
74 //////////////////// I2C ////////////////////////////
75 I2C_SDAT, // I2C Data
76 I2C_SCLK, // I2C Clock
77 //////////////////// PS2 ////////////////////////////
78 PS2_DAT, // PS2 Data
79 PS2_CLK, // PS2 Clock
80 //////////////////// VGA ////////////////////////////
81 VGA_HS, // VGA H_SYNC
82 VGA_VS, // VGA V_SYNC
83 VGA_R, // VGA Red[3:0]
84 VGA_G, // VGA Green[3:0]
85 VGA_B, // VGA Blue[3:0]
86 //////////////// Audio CODEC ////////////////////////
87 AUD_ADCLRCK, // Audio CODEC ADC LR Clock
88 AUD_ADCDAT, // Audio CODEC ADC Data
89 AUD_DACLRCK, // Audio CODEC DAC LR Clock
90 AUD_DACDAT, // Audio CODEC DAC Data
91 AUD_BCLK, // Audio CODEC Bit-Stream Clock
92 AUD_XCK, // Audio CODEC Chip Clock
93 //////////////////// GPIO ////////////////////////////
94 GPIO_0, // GPIO Connection 0
95 GPIO_1 // GPIO Connection 1
96 );
97
98 //////////////////////// Clock Input ////////////////////////
99 input [1:0] CLOCK_24; // 24 MHz
100 input [1:0] CLOCK_27; // 27 MHz
101 input CLOCK_50; // 50 MHz
102 input EXT_CLOCK; // External Clock
103 //////////////////////// Push Button ////////////////////////
104 input [3:0] KEY; // Pushbutton[3:0]
105 //////////////////////// DPDT Switch ////////////////////////
106 input [9:0] SW; // Toggle Switch[9:0]
107 //////////////////////// 7-SEG Dispaly ////////////////////////
108 output [6:0] HEX0; // Seven Segment Digit 0
109 output [6:0] HEX1; // Seven Segment Digit 1
110 output [6:0] HEX2; // Seven Segment Digit 2
111 output [6:0] HEX3; // Seven Segment Digit 3
112 //////////////////////////// LED ////////////////////////////
113 output [7:0] LEDG; // LED Green[7:0]
114 output [9:0] LEDR; // LED Red[9:0]
115 //////////////////////////// UART ////////////////////////////
116 output UART_TXD; // UART Transmitter
117 input UART_RXD; // UART Receiver
118 /////////////////////// SDRAM Interface ////////////////////////
119 inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
120 output [11:0] DRAM_ADDR; // SDRAM Address bus 12 Bits
121 output DRAM_LDQM; // SDRAM Low-byte Data Mask
122 output DRAM_UDQM; // SDRAM High-byte Data Mask
123 output DRAM_WE_N; // SDRAM Write Enable
124 output DRAM_CAS_N; // SDRAM Column Address Strobe
125 output DRAM_RAS_N; // SDRAM Row Address Strobe
126 output DRAM_CS_N; // SDRAM Chip Select
127 output DRAM_BA_0; // SDRAM Bank Address 0
128 output DRAM_BA_1; // SDRAM Bank Address 0
129 output DRAM_CLK; // SDRAM Clock
130 output DRAM_CKE; // SDRAM Clock Enable
131 //////////////////////// Flash Interface ////////////////////////
132 inout [7:0] FL_DQ; // FLASH Data bus 8 Bits
133 output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
134 output FL_WE_N; // FLASH Write Enable
135 output FL_RST_N; // FLASH Reset
136 output FL_OE_N; // FLASH Output Enable
137 output FL_CE_N; // FLASH Chip Enable
138 //////////////////////// SRAM Interface ////////////////////////
139 inout [15:0] SRAM_DQ; // SRAM Data bus 16 Bits
140 output [17:0] SRAM_ADDR; // SRAM Address bus 18 Bits
141 output SRAM_UB_N; // SRAM High-byte Data Mask
142 output SRAM_LB_N; // SRAM Low-byte Data Mask
143 output SRAM_WE_N; // SRAM Write Enable
144 output SRAM_CE_N; // SRAM Chip Enable
145 output SRAM_OE_N; // SRAM Output Enable
146 //////////////////// SD Card Interface ////////////////////////
147 inout SD_DAT; // SD Card Data
148 inout SD_DAT3; // SD Card Data 3
149 inout SD_CMD; // SD Card Command Signal
150 output SD_CLK; // SD Card Clock
151 //////////////////////// I2C ////////////////////////////////
152 inout I2C_SDAT; // I2C Data
153 output I2C_SCLK; // I2C Clock
154 //////////////////////// PS2 ////////////////////////////////
155 input PS2_DAT; // PS2 Data
156 input PS2_CLK; // PS2 Clock
157 //////////////////// USB JTAG link ////////////////////////////
158 input TDI; // CPLD -> FPGA (data in)
159 input TCK; // CPLD -> FPGA (clk)
160 input TCS; // CPLD -> FPGA (CS)
161 output TDO; // FPGA -> CPLD (data out)
162 //////////////////////// VGA ////////////////////////////
163 output VGA_HS; // VGA H_SYNC
164 output VGA_VS; // VGA V_SYNC
165 output [3:0] VGA_R; // VGA Red[3:0]
166 output [3:0] VGA_G; // VGA Green[3:0]
167 output [3:0] VGA_B; // VGA Blue[3:0]
168 //////////////////// Audio CODEC ////////////////////////////
169 inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
170 input AUD_ADCDAT; // Audio CODEC ADC Data
171 inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
172 output AUD_DACDAT; // Audio CODEC DAC Data
173 inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
174 output AUD_XCK; // Audio CODEC Chip Clock
175 //////////////////////// GPIO ////////////////////////////////
176 inout [35:0] GPIO_0; // GPIO Connection 0
177 inout [35:0] GPIO_1; // GPIO Connection 1
178
179 // Turn off all display
180 assign HEX0 = 7'h7F;
181 assign HEX1 = 7'h7F;
182 assign HEX2 = 7'h7F;
183 assign HEX3 = 7'h7F;
184// assign LEDG = 8'h00;
185 assign LEDR = 10'h000;
186
187 // All inout port turn to tri-state
188 assign DRAM_DQ = 16'bz;
189 assign FL_DQ = 8'bz;
190 assign SRAM_DQ = 16'bz;
191 assign SD_DAT = 1'bz;
192 assign I2C_SDAT = 1'bz;
193 assign AUD_ADCLRCK = 1'bz;
194 assign AUD_DACLRCK = 1'bz;
195 assign AUD_BCLK = 1'bz;
196 assign GPIO_0 = 36'bz;
197// assign GPIO_1 = 36'bz;
198
199
200 reg [9:0] osc_counter;
201 reg [25:0] hst_counter;
202
203 reg osc_reset;
204 reg osc_bit_num;
205 wire [9:0] osc_start_addr;
206 reg [9:0] osc_addr;
207 wire [15:0] osc_q;
208
209 reg hst_reset;
210 reg [1:0] hst_bit_num;
211 reg [11:0] hst_addr;
212 wire [31:0] hst_q;
213
214 reg [3:0] state0, state1, state2;
215 reg adc_fifo_rdreq;
216 wire adc_fifo_rdempty;
217 reg adc_fifo_aclr;
218 reg rd_uart, wr_uart;
219 wire tx_full, rx_empty;
220
221 wire [7:0] RxD_data;
222 reg [7:0] TxD_data;
223
224 wire [4:0] led;
225
226 reg adc_data_ready;
227 wire adc_dr, adc_or;
228// wire [11:0] adc_data;
229 reg [11:0] adc_data;
230 wire [11:0] raw_data;
231 wire [11:0] uwt_data;
232 wire [1:0] uwt_flag;
233
234 assign GPIO_1[21:0]= 22'bz;
235 assign adc_or = GPIO_1[35];
236// assign adc_data = GPIO_1[34:23];
237// assign adc_dr = GPIO_1[22];
238 assign adc_dr = CLOCK_24[0];
239
240 assign LEDG = {3'h0, led};
241
242 assign led[4] = hst_counter[23];
243
244 uart uart_unit (
245 .clk(CLOCK_50),
246 .reset(1'b0),
247 .rd_uart(rd_uart),
248 .wr_uart(wr_uart),
249 .rx(UART_RXD),
250 .w_data(TxD_data),
251 .tx_full(tx_full),
252 .rx_empty(rx_empty),
253 .r_data(RxD_data),
254 .tx(UART_TXD));
255
256 adc_fifo adc_fifo_unit (
257 .adc_dr(adc_dr),
258 .adc_or(adc_or),
259 .adc_data(adc_data),
260 .aclr(adc_fifo_aclr),
261 .rdclk(CLOCK_50),
262 .rdreq(adc_fifo_rdreq),
263 .rdempty(adc_fifo_rdempty),
264 .raw_data(raw_data),
265 .uwt_data({uwt_flag, uwt_data}));
266
267 histogram histogram_unit (
268 .clk(CLOCK_50),
269 .reset(hst_reset),
270 .data_ready(adc_data_ready),
271 .data(raw_data),
272 .address(hst_addr),
273 .q(hst_q),
274 .led(led[3:0])
275 );
276
277 oscilloscope oscilloscope_unit (
278 .clk(CLOCK_50),
279 .reset(osc_reset),
280 .data_ready(adc_data_ready),
281 .raw_data(raw_data),
282 .uwt_data(uwt_data),
283 .threshold(16'd100),
284 .address(osc_addr),
285 .start_address(osc_start_addr),
286 .q(osc_q)
287 );
288
289
290 always @ (posedge CLOCK_50)
291 begin
292
293 case (state0)
294 1:
295 begin
296 if (~adc_fifo_rdempty)
297 begin
298 adc_fifo_rdreq <= 1'b1;
299 adc_data_ready <= 1'b1;
300 state0 <= 4'd2;
301 end
302 end
303
304 2:
305 begin
306 adc_fifo_rdreq <= 1'b0;
307 adc_data_ready <= 1'b0;
308 state0 <= 4'd1;
309 end
310
311 default:
312 begin
313 state0 <= 4'd1;
314 end
315 endcase
316
317 case (state1)
318 1:
319 begin
320 rd_uart <= 1'b0;
321 hst_reset <= 1'b0;
322 osc_reset <= 1'b0;
323 state1 <= 4'd2;
324 end
325
326 2:
327 begin
328 if (~rx_empty)
329 begin
330 rd_uart <= 1'b1;
331 case (RxD_data)
332 8'h30:
333 begin
334 hst_reset <= 1'b1;
335 state1 <= 4'd1;
336 end
337 8'h31: state1 <= 4'd3;
338 8'h32:
339 begin
340 osc_reset <= 1'b1;
341 state1 <= 4'd1;
342 end
343 8'h33: state1 <= 4'd7;
344 endcase
345 end
346 else
347 begin
348 rd_uart <= 1'b0;
349 end
350 end
351
352 3:
353 begin
354 // start hst transfer
355 rd_uart <= 1'b0;
356 hst_addr <= 12'h0;
357 hst_bit_num <= 2'd0;
358 state1 <= 4'd4;
359 end
360
361 4:
362 begin
363 case (hst_bit_num)
364 2'd0: TxD_data <= hst_q[7:0];
365 2'd1: TxD_data <= hst_q[15:8];
366 2'd2: TxD_data <= hst_q[23:16];
367 2'd3: TxD_data <= hst_q[31:24];
368// 2'd0: TxD_data <= 8'd255;
369// 2'd1: TxD_data <= 8'd0;
370// 2'd2: TxD_data <= 8'd0;
371// 2'd3: TxD_data <= 8'd0;
372 endcase
373 wr_uart <= 0;
374 state1 <= 4'd5;
375 end
376
377 5:
378 begin
379 if (~tx_full)
380 begin
381 wr_uart <= 1;
382 state1 <= 4'd6;
383 end
384 end
385
386 6:
387 begin
388 wr_uart <= 0;
389 if (&hst_bit_num)
390 begin
391 hst_bit_num <= 2'd0;
392 if (&hst_addr)
393 begin
394 state1 <= 4'd1;
395 end
396 else
397 begin
398 hst_addr <= hst_addr + 12'd1;
399 state1 <= 4'd4;
400 end
401 end
402 else
403 begin
404 hst_bit_num <= hst_bit_num + 2'd1;
405 state1 <= 4'd4;
406 end
407 end
408
409
410 7:
411 begin
412 // start osc transfer
413 rd_uart <= 1'b0;
414 osc_addr <= osc_start_addr;
415 osc_bit_num <= 1'd0;
416 osc_counter <= 10'd0;
417 state1 <= 4'd8;
418 end
419
420 8:
421 begin
422 case(osc_bit_num)
423 1'd0: TxD_data <= osc_q[7:0];
424 1'd1: TxD_data <= osc_q[15:8];
425 endcase
426 wr_uart <= 0;
427 state1 <= 4'd9;
428 end
429
430 9:
431 begin
432 if (~tx_full)
433 begin
434 wr_uart <= 1;
435 state1 <= 4'd10;
436 end
437 end
438
439 10:
440 begin
441 wr_uart <= 0;
442 if (osc_bit_num)
443 begin
444 osc_bit_num <= 1'd0;
445 if (&osc_counter)
446 begin
447 state1 <= 4'd1;
448 end
449 else
450 begin
451 osc_addr <= osc_addr + 10'd1;
452 osc_counter <= osc_counter + 10'd1;
453 state1 <= 4'd8;
454 end
455 end
456 else
457 begin
458 osc_bit_num <= osc_bit_num + 1'd1;
459 state1 <= 4'd8;
460 end
461 end
462
463 default:
464 begin
465 // default state is the first one
466 state1 <= 4'd1;
467 end
468 endcase
469 end
470
471 always @ (posedge adc_dr)
472 begin
473 case (state2)
474 1:
475 begin
476 adc_data <= 12'd0;
477 state2 <= 4'd2;
478 end
479
480 2:
481 begin
482 adc_data <= 12'd1024;
483 state2 <= 4'd3;
484 end
485
486 3:
487 begin
488 adc_data <= 12'd2048;
489 state2 <= 4'd4;
490 end
491
492 4:
493 begin
494 adc_data <= 12'd3072;
495 state2 <= 4'd5;
496 end
497
498 5:
499 begin
500 adc_data <= 12'd4095;
501 state2 <= 4'd1;
502 end
503
504 default:
505 begin
506 state2 <= 4'd1;
507 end
508 endcase
509 end
510
511endmodule
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