source: trunk/FirmwareFX2/usbjtag.c@ 201

Last change on this file since 201 was 137, checked in by demin, 14 years ago

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File size: 12.9 KB
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1/*-----------------------------------------------------------------------------
2 * Code that turns a Cypress FX2 USB Controller into an USB JTAG adapter
3 *-----------------------------------------------------------------------------
4 * Copyright (C) 2005..2007 Kolja Waschk, ixo.de
5 *-----------------------------------------------------------------------------
6 * Check hardware.h/.c if it matches your hardware configuration (e.g. pinout).
7 * Changes regarding USB identification should be made in product.inc!
8 *-----------------------------------------------------------------------------
9 * This code is part of usbjtag. usbjtag is free software; you can redistribute
10 * it and/or modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the License,
12 * or (at your option) any later version. usbjtag is distributed in the hope
13 * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. You should have received a
16 * copy of the GNU General Public License along with this program in the file
17 * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
18 * St, Fifth Floor, Boston, MA 02110-1301 USA
19 *-----------------------------------------------------------------------------
20 */
21
22#include "isr.h"
23#include "timer.h"
24#include "delay.h"
25#include "fx2regs.h"
26#include "fx2utils.h"
27#include "usb_common.h"
28#include "usb_descriptors.h"
29#include "usb_requests.h"
30
31#include "syncdelay.h"
32
33#include "eeprom.h"
34#include "hardware.h"
35
36//-----------------------------------------------------------------------------
37// Define USE_MOD256_OUTBUFFER:
38// Saves about 256 bytes in code size, improves speed a little.
39// A further optimization could be not to use an extra output buffer at
40// all, but to write directly into EP1INBUF. Not implemented yet. When
41// downloading large amounts of data _to_ the target, there is no output
42// and thus the output buffer isn't used at all and doesn't slow down things.
43
44#define USE_MOD256_OUTBUFFER 1
45
46//-----------------------------------------------------------------------------
47// Global data
48
49typedef bit BOOL;
50#define FALSE 0
51#define TRUE 1
52static BOOL Running;
53static BOOL WriteOnly;
54
55static BYTE ClockBytes;
56static WORD Pending;
57
58#ifdef USE_MOD256_OUTBUFFER
59 static BYTE FirstDataInOutBuffer;
60 static BYTE FirstFreeInOutBuffer;
61#else
62 static WORD FirstDataInOutBuffer;
63 static WORD FirstFreeInOutBuffer;
64#endif
65
66#ifdef USE_MOD256_OUTBUFFER
67 /* Size of output buffer must be exactly 256 */
68 #define OUTBUFFER_LEN 0x100
69 /* Output buffer must begin at some address with lower 8 bits all zero */
70 xdata at 0xE000 BYTE OutBuffer[OUTBUFFER_LEN];
71#else
72 #define OUTBUFFER_LEN 0x200
73 static xdata BYTE OutBuffer[OUTBUFFER_LEN];
74#endif
75
76//-----------------------------------------------------------------------------
77
78void usb_jtag_init(void) // Called once at startup
79{
80 WORD tmp;
81
82 Running = FALSE;
83 ClockBytes = 0;
84 Pending = 0;
85 WriteOnly = TRUE;
86 FirstDataInOutBuffer = 0;
87 FirstFreeInOutBuffer = 0;
88
89 ProgIO_Init();
90
91 ProgIO_Enable();
92
93 // Make Timer2 reload at 100 Hz to trigger Keepalive packets
94
95 tmp = 65536 - ( 48000000 / 12 / 100 );
96 RCAP2H = tmp >> 8;
97 RCAP2L = tmp & 0xFF;
98 CKCON = 0; // Default Clock
99 T2CON = 0x04; // Auto-reload mode using internal clock, no baud clock.
100
101 // Enable Autopointer
102
103 EXTACC = 1; // Enable
104 APTR1FZ = 1; // Don't freeze
105 APTR2FZ = 1; // Don't freeze
106
107 // define endpoint configuration
108
109 REVCTL = 0x03; SYNCDELAY; // Allow FW access to FIFO buffer
110
111 EP1OUTCFG = 0xA0; SYNCDELAY; // Endpoint 1 Type Bulk
112 EP1INCFG = 0xA0; SYNCDELAY; // Endpoint 1 Type Bulk
113
114 EP2CFG = 0xA2; SYNCDELAY; // Endpoint 2 ON, OUT, BULK, 512, Buffer 2x
115 EP6CFG = 0xE3; SYNCDELAY; // Endpoint 6 ON, IN, BULK, 512, Buffer 3x
116 EP8CFG = 0xA0; SYNCDELAY; // Endpoint 8 ON, OUT, BULK, 512, Buffer 2x
117
118 EP4CFG = 0x20; SYNCDELAY; // Endpoint 4 OFF, OUT, BULK, 512, Buffer 2x
119
120 FIFORESET = 0x80; SYNCDELAY; // From now on, NAK all
121 FIFORESET = 0x82; SYNCDELAY; // Reset Endpoint 2 FIFO
122 FIFORESET = 0x84; SYNCDELAY; // Reset Endpoint 4 FIFO
123 FIFORESET = 0x86; SYNCDELAY; // Reset Endpoint 6 FIFO
124 FIFORESET = 0x88; SYNCDELAY; // Reset Endpoint 8 FIFO
125 FIFORESET = 0x00; SYNCDELAY; // Restore normal behaviour
126
127 OUTPKTEND = 0x82; SYNCDELAY; // Arm Endpoint 2 buffers to "prime the pump"
128 OUTPKTEND = 0x82; SYNCDELAY;
129 OUTPKTEND = 0x88; SYNCDELAY; // Arm Endpoint 8 buffers to "prime the pump"
130 OUTPKTEND = 0x88; SYNCDELAY;
131
132 REVCTL = 0x00; SYNCDELAY; // Reset FW access to FIFO buffer, enable auto-arming when AUTOOUT is switched to 1
133
134 EP2FIFOCFG = 0x00; SYNCDELAY;
135 EP4FIFOCFG = 0x00; SYNCDELAY;
136 EP6FIFOCFG = bmAUTOIN; SYNCDELAY;
137 EP8FIFOCFG = bmAUTOOUT; SYNCDELAY;
138
139 EP8AUTOINLENH = 0x02; SYNCDELAY; // Auto-commit 512-byte packets
140 EP8AUTOINLENL = 0x00; SYNCDELAY;
141
142 PINFLAGSAB = 0xEB; SYNCDELAY; // 1111_1010 => FLAGA = EMPTY flag for EP6; FLAGB = FULL flag for EP8
143 IOD |= (1 << 4); SYNCDELAY; // LED turned off by default
144}
145
146void OutputByte(BYTE d)
147{
148#ifdef USE_MOD256_OUTBUFFER
149 OutBuffer[FirstFreeInOutBuffer] = d;
150 FirstFreeInOutBuffer = ( FirstFreeInOutBuffer + 1 ) & 0xFF;
151#else
152 OutBuffer[FirstFreeInOutBuffer++] = d;
153 if(FirstFreeInOutBuffer >= OUTBUFFER_LEN) FirstFreeInOutBuffer = 0;
154#endif
155 Pending++;
156}
157
158//-----------------------------------------------------------------------------
159// usb_jtag_activity does most of the work. It now happens to behave just like
160// the combination of FT245BM and Altera-programmed EPM7064 CPLD in Altera's
161// USB-Blaster. The CPLD knows two major modes: Bit banging mode and Byte
162// shift mode. It starts in Bit banging mode. While bytes are received
163// from the host on EP2OUT, each byte B of them is processed as follows:
164//
165// Please note: nCE, nCS, LED pins and DATAOUT actually aren't supported here.
166// Support for these would be required for AS/PS mode and isn't too complicated,
167// but I haven't had the time yet.
168//
169// Bit banging mode:
170//
171// 1. Remember bit 6 (0x40) in B as the "Read bit".
172//
173// 2. If bit 7 (0x40) is set, switch to Byte shift mode for the coming
174// X bytes ( X := B & 0x3F ), and don't do anything else now.
175//
176// 3. Otherwise, set the JTAG signals as follows:
177// TCK/DCLK high if bit 0 was set (0x01), otherwise low
178// TMS/nCONFIG high if bit 1 was set (0x02), otherwise low
179// nCE high if bit 2 was set (0x04), otherwise low
180// nCS high if bit 3 was set (0x08), otherwise low
181// TDI/ASDI/DATA0 high if bit 4 was set (0x10), otherwise low
182// Output Enable/LED active if bit 5 was set (0x20), otherwise low
183//
184// 4. If "Read bit" (0x40) was set, record the state of TDO(CONF_DONE) and
185// DATAOUT(nSTATUS) pins and put it as a byte ((DATAOUT<<1)|TDO) in the
186// output FIFO _to_ the host (the code here reads TDO only and assumes
187// DATAOUT=1)
188//
189// Byte shift mode:
190//
191// 1. Load shift register with byte from host
192//
193// 2. Do 8 times (i.e. for each bit of the byte; implemented in shift.a51)
194// 2a) if nCS=1, set carry bit from TDO, else set carry bit from DATAOUT
195// 2b) Rotate shift register through carry bit
196// 2c) TDI := Carry bit
197// 2d) Raise TCK, then lower TCK.
198//
199// 3. If "Read bit" was set when switching into byte shift mode,
200// record the shift register content and put it into the FIFO
201// _to_ the host.
202//
203// Some more (minor) things to consider to emulate the FT245BM:
204//
205// a) The FT245BM seems to transmit just packets of no more than 64 bytes
206// (which perfectly matches the USB spec). Each packet starts with
207// two non-data bytes (I use 0x31,0x60 here). A USB sniffer on Windows
208// might show a number of packets to you as if it was a large transfer
209// because of the way that Windows understands it: it _is_ a large
210// transfer until terminated with an USB packet smaller than 64 byte.
211//
212// b) The Windows driver expects to get some data packets (with at least
213// the two leading bytes 0x31,0x60) immediately after "resetting" the
214// FT chip and then in regular intervals. Otherwise a blue screen may
215// appear... In the code below, I make sure that every 10ms there is
216// some packet.
217//
218// c) Vendor specific commands to configure the FT245 are mostly ignored
219// in my code. Only those for reading the EEPROM are processed. See
220// DR_GetStatus and DR_VendorCmd below for my implementation.
221//
222// All other TD_ and DR_ functions remain as provided with CY3681.
223//
224//-----------------------------------------------------------------------------
225
226void usb_jtag_activity(void) // Called repeatedly while the device is idle
227{
228 if(!Running) return;
229
230 ProgIO_Poll();
231
232 if(!(EP1INCS & bmEPBUSY))
233 {
234 if(Pending > 0)
235 {
236 BYTE o, n;
237
238 AUTOPTRH2 = MSB( EP1INBUF );
239 AUTOPTRL2 = LSB( EP1INBUF );
240
241 XAUTODAT2 = 0x31;
242 XAUTODAT2 = 0x60;
243
244 if(Pending > 0x3E) { n = 0x3E; Pending -= n; }
245 else { n = Pending; Pending = 0; };
246
247 o = n;
248
249#ifdef USE_MOD256_OUTBUFFER
250 APTR1H = MSB( OutBuffer );
251 APTR1L = FirstDataInOutBuffer;
252 while(n--)
253 {
254 XAUTODAT2 = XAUTODAT1;
255 APTR1H = MSB( OutBuffer ); // Stay within 256-Byte-Buffer
256 };
257 FirstDataInOutBuffer = APTR1L;
258#else
259 APTR1H = MSB( &(OutBuffer[FirstDataInOutBuffer]) );
260 APTR1L = LSB( &(OutBuffer[FirstDataInOutBuffer]) );
261 while(n--)
262 {
263 XAUTODAT2 = XAUTODAT1;
264
265 if(++FirstDataInOutBuffer >= OUTBUFFER_LEN)
266 {
267 FirstDataInOutBuffer = 0;
268 APTR1H = MSB( OutBuffer );
269 APTR1L = LSB( OutBuffer );
270 };
271 };
272#endif
273 SYNCDELAY;
274 EP1INBC = 2 + o;
275 TF2 = 1; // Make sure there will be a short transfer soon
276 }
277 else if(TF2)
278 {
279 EP1INBUF[0] = 0x31;
280 EP1INBUF[1] = 0x60;
281 SYNCDELAY;
282 EP1INBC = 2;
283 TF2 = 0;
284 };
285 };
286
287 if(!(EP2468STAT & bmEP2EMPTY) && (Pending < OUTBUFFER_LEN-0x3F))
288 {
289 WORD i, n = EP2BCL|EP2BCH<<8;
290
291 APTR1H = MSB( EP2FIFOBUF );
292 APTR1L = LSB( EP2FIFOBUF );
293
294 for(i=0;i<n;)
295 {
296 if(ClockBytes > 0)
297 {
298 WORD m;
299
300 m = n-i;
301 if(ClockBytes < m) m = ClockBytes;
302 ClockBytes -= m;
303 i += m;
304
305 /* Shift out 8 bits from d */
306
307 if(WriteOnly) /* Shift out 8 bits from d */
308 {
309 while(m--) ProgIO_ShiftOut(XAUTODAT1);
310 }
311 else /* Shift in 8 bits at the other end */
312 {
313 while(m--) OutputByte(ProgIO_ShiftInOut(XAUTODAT1));
314 }
315 }
316 else
317 {
318 BYTE d = XAUTODAT1;
319 WriteOnly = (d & bmBIT6) ? FALSE : TRUE;
320
321 if(d & bmBIT7)
322 {
323 /* Prepare byte transfer, do nothing else yet */
324
325 ClockBytes = d & 0x3F;
326 }
327 else
328 {
329 if(WriteOnly)
330 ProgIO_Set_State(d);
331 else
332 OutputByte(ProgIO_Set_Get_State(d));
333 };
334 i++;
335 };
336 };
337
338 SYNCDELAY;
339 EP2BCL = 0x80; // Re-arm endpoint 2
340 };
341}
342
343//-----------------------------------------------------------------------------
344// Handler for Vendor Requests (
345//-----------------------------------------------------------------------------
346
347unsigned char app_vendor_cmd(void)
348{
349 // because of fx2/usb_common.c, this code returns nonzero on success
350 // OUT requests. Pretend we handle them all...
351
352 if ((bRequestType & bmRT_DIR_MASK) == bmRT_DIR_OUT)
353 {
354 if(bRequest == RQ_GET_STATUS)
355 {
356 Running = 1;
357 }
358
359 return 1;
360 }
361
362 // IN requests.
363
364 if(bRequest == 0x90)
365 {
366 BYTE addr = (wIndexL<<1) & 0x7F;
367 EP0BUF[0] = eeprom[addr];
368 EP0BUF[1] = eeprom[addr+1];
369 }
370 else
371 {
372 // dummy data
373 EP0BUF[0] = 0x36;
374 EP0BUF[1] = 0x83;
375 }
376
377 EP0BCH = 0;
378 EP0BCL = (wLengthL<2) ? wLengthL : 2; // Arm endpoint with # bytes to transfer
379
380 return 1;
381}
382
383//-----------------------------------------------------------------------------
384
385static void main_loop(void)
386{
387 while(1)
388 {
389 if(usb_setup_packet_avail()) usb_handle_setup_packet();
390 usb_jtag_activity();
391 }
392}
393
394//-----------------------------------------------------------------------------
395
396void main(void)
397{
398 EA = 0; // disable all interrupts
399
400 usb_jtag_init();
401 eeprom_init();
402 setup_autovectors();
403 usb_install_handlers();
404
405
406 EA = 1; // enable interrupts
407
408 fx2_renumerate(); // simulates disconnect / reconnect
409
410 main_loop();
411}
412
413
414
415
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