source: trunk/FirmwareFX2/usbjtag.c@ 16

Last change on this file since 16 was 4, checked in by demin, 15 years ago

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[4]1/*-----------------------------------------------------------------------------
2 * Code that turns a Cypress FX2 USB Controller into an USB JTAG adapter
3 *-----------------------------------------------------------------------------
4 * Copyright (C) 2005..2007 Kolja Waschk, ixo.de
5 *-----------------------------------------------------------------------------
6 * Check hardware.h/.c if it matches your hardware configuration (e.g. pinout).
7 * Changes regarding USB identification should be made in product.inc!
8 *-----------------------------------------------------------------------------
9 * This code is part of usbjtag. usbjtag is free software; you can redistribute
10 * it and/or modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the License,
12 * or (at your option) any later version. usbjtag is distributed in the hope
13 * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. You should have received a
16 * copy of the GNU General Public License along with this program in the file
17 * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
18 * St, Fifth Floor, Boston, MA 02110-1301 USA
19 *-----------------------------------------------------------------------------
20 */
21
22#include "isr.h"
23#include "timer.h"
24#include "delay.h"
25#include "fx2regs.h"
26#include "fx2utils.h"
27#include "usb_common.h"
28#include "usb_descriptors.h"
29#include "usb_requests.h"
30
31#include "syncdelay.h"
32
33#include "eeprom.h"
34#include "hardware.h"
35
36#include "spi.h"
37
38//-----------------------------------------------------------------------------
39// Define USE_MOD256_OUTBUFFER:
40// Saves about 256 bytes in code size, improves speed a little.
41// A further optimization could be not to use an extra output buffer at
42// all, but to write directly into EP1INBUF. Not implemented yet. When
43// downloading large amounts of data _to_ the target, there is no output
44// and thus the output buffer isn't used at all and doesn't slow down things.
45
46#define USE_MOD256_OUTBUFFER 1
47
48//-----------------------------------------------------------------------------
49// Global data
50
51typedef bit BOOL;
52#define FALSE 0
53#define TRUE 1
54static BOOL Running;
55static BOOL WriteOnly;
56
57static BYTE ClockBytes;
58static WORD Pending;
59
60#ifdef USE_MOD256_OUTBUFFER
61 static BYTE FirstDataInOutBuffer;
62 static BYTE FirstFreeInOutBuffer;
63#else
64 static WORD FirstDataInOutBuffer;
65 static WORD FirstFreeInOutBuffer;
66#endif
67
68#ifdef USE_MOD256_OUTBUFFER
69 /* Size of output buffer must be exactly 256 */
70 #define OUTBUFFER_LEN 0x100
71 /* Output buffer must begin at some address with lower 8 bits all zero */
72 xdata at 0xE000 BYTE OutBuffer[OUTBUFFER_LEN];
73#else
74 #define OUTBUFFER_LEN 0x200
75 static xdata BYTE OutBuffer[OUTBUFFER_LEN];
76#endif
77
78//-----------------------------------------------------------------------------
79
80void usb_jtag_init(void) // Called once at startup
81{
82 WORD tmp;
83
84 Running = FALSE;
85 ClockBytes = 0;
86 Pending = 0;
87 WriteOnly = TRUE;
88 FirstDataInOutBuffer = 0;
89 FirstFreeInOutBuffer = 0;
90
91 ProgIO_Init();
92
93 ProgIO_Enable();
94
95 // Make Timer2 reload at 100 Hz to trigger Keepalive packets
96 tmp = 65536 - ( 48000000 / 12 / 100 );
97 RCAP2H = tmp >> 8;
98 RCAP2L = tmp & 0xFF;
99 CKCON = 0; // Default Clock
100 T2CON = 0x04; // Auto-reload mode using internal clock, no baud clock.
101
102 // Enable Autopointer
103 EXTACC = 1; // Enable
104 APTR1FZ = 1; // Don't freeze
105 APTR2FZ = 1; // Don't freeze
106
107 // define endpoint configuration
108
109 REVCTL = 3; SYNCDELAY; // Allow FW access to FIFO buffer
110 FIFORESET = 0x80; SYNCDELAY; // From now on, NAK all, reset all FIFOS
111 FIFORESET = 0x02; SYNCDELAY; // Reset FIFO 2
112 FIFORESET = 0x04; SYNCDELAY; // Reset FIFO 4
113 FIFORESET = 0x06; SYNCDELAY; // Reset FIFO 6
114 FIFORESET = 0x08; SYNCDELAY; // Reset FIFO 8
115 FIFORESET = 0x00; SYNCDELAY; // Restore normal behaviour
116
117 EP1OUTCFG = 0xA0; SYNCDELAY; // Endpoint 1 Type Bulk
118 EP1INCFG = 0xA0; SYNCDELAY; // Endpoint 1 Type Bulk
119
120 EP2FIFOCFG = 0x00; SYNCDELAY; // Endpoint 2
121 EP2CFG = 0xA2; SYNCDELAY; // Endpoint 2 Valid, Out, Type Bulk, Double buffered
122
123 EP4FIFOCFG = 0x00; SYNCDELAY; // Endpoint 4 not used
124 EP4CFG = 0xA0; SYNCDELAY; // Endpoint 4 not used
125
126 REVCTL = 0; SYNCDELAY; // Reset FW access to FIFO buffer, enable auto-arming when AUTOOUT is switched to 1
127
128 EP6CFG = 0xA2; SYNCDELAY; // Out endpoint, Bulk, Double buffering
129 EP6FIFOCFG = 0x00; SYNCDELAY; // Firmware has to see a rising edge on auto bit to enable auto arming
130 EP6FIFOCFG = bmAUTOOUT | bmWORDWIDE; SYNCDELAY; // Endpoint 6 used for user communicationn, auto commitment, 16 bits data bus
131
132 EP8CFG = 0xE0; SYNCDELAY; // In endpoint, Bulk
133 EP8FIFOCFG = 0x00; SYNCDELAY; // Firmware has to see a rising edge on auto bit to enable auto arming
134 EP8FIFOCFG = bmAUTOIN | bmWORDWIDE; SYNCDELAY; // Endpoint 8 used for user communication, auto commitment, 16 bits data bus
135
136 EP8AUTOINLENH = 0x00; SYNCDELAY; // Size in bytes of the IN data automatically commited (64 bytes here, but changed dynamically depending on the connection)
137 EP8AUTOINLENL = 0x40; SYNCDELAY; // Can use signal PKTEND if you want to commit a shorter packet
138
139 // Out endpoints do not come up armed
140 // Since the defaults are double buffered we must write dummy byte counts twice
141 EP2BCL = 0x80; SYNCDELAY; // Arm EP2OUT by writing byte count w/skip.=
142 EP4BCL = 0x80; SYNCDELAY;
143 EP2BCL = 0x80; SYNCDELAY; // Arm EP4OUT by writing byte count w/skip.=
144 EP4BCL = 0x80; SYNCDELAY;
145
146 // JTAG from FX2 enabled by default
147 IOC |= (1 << 7);
148
149 // Put the system in high speed by default (REM: USB-Blaster is in full speed)
150 // This can be changed by vendor commands
151 CT1 &= ~0x02;
152}
153
154void OutputByte(BYTE d)
155{
156#ifdef USE_MOD256_OUTBUFFER
157 OutBuffer[FirstFreeInOutBuffer] = d;
158 FirstFreeInOutBuffer = ( FirstFreeInOutBuffer + 1 ) & 0xFF;
159#else
160 OutBuffer[FirstFreeInOutBuffer++] = d;
161 if(FirstFreeInOutBuffer >= OUTBUFFER_LEN) FirstFreeInOutBuffer = 0;
162#endif
163 Pending++;
164}
165
166//-----------------------------------------------------------------------------
167// usb_jtag_activity does most of the work. It now happens to behave just like
168// the combination of FT245BM and Altera-programmed EPM7064 CPLD in Altera's
169// USB-Blaster. The CPLD knows two major modes: Bit banging mode and Byte
170// shift mode. It starts in Bit banging mode. While bytes are received
171// from the host on EP2OUT, each byte B of them is processed as follows:
172//
173// Please note: nCE, nCS, LED pins and DATAOUT actually aren't supported here.
174// Support for these would be required for AS/PS mode and isn't too complicated,
175// but I haven't had the time yet.
176//
177// Bit banging mode:
178//
179// 1. Remember bit 6 (0x40) in B as the "Read bit".
180//
181// 2. If bit 7 (0x40) is set, switch to Byte shift mode for the coming
182// X bytes ( X := B & 0x3F ), and don't do anything else now.
183//
184// 3. Otherwise, set the JTAG signals as follows:
185// TCK/DCLK high if bit 0 was set (0x01), otherwise low
186// TMS/nCONFIG high if bit 1 was set (0x02), otherwise low
187// nCE high if bit 2 was set (0x04), otherwise low
188// nCS high if bit 3 was set (0x08), otherwise low
189// TDI/ASDI/DATA0 high if bit 4 was set (0x10), otherwise low
190// Output Enable/LED active if bit 5 was set (0x20), otherwise low
191//
192// 4. If "Read bit" (0x40) was set, record the state of TDO(CONF_DONE) and
193// DATAOUT(nSTATUS) pins and put it as a byte ((DATAOUT<<1)|TDO) in the
194// output FIFO _to_ the host (the code here reads TDO only and assumes
195// DATAOUT=1)
196//
197// Byte shift mode:
198//
199// 1. Load shift register with byte from host
200//
201// 2. Do 8 times (i.e. for each bit of the byte; implemented in shift.a51)
202// 2a) if nCS=1, set carry bit from TDO, else set carry bit from DATAOUT
203// 2b) Rotate shift register through carry bit
204// 2c) TDI := Carry bit
205// 2d) Raise TCK, then lower TCK.
206//
207// 3. If "Read bit" was set when switching into byte shift mode,
208// record the shift register content and put it into the FIFO
209// _to_ the host.
210//
211// Some more (minor) things to consider to emulate the FT245BM:
212//
213// a) The FT245BM seems to transmit just packets of no more than 64 bytes
214// (which perfectly matches the USB spec). Each packet starts with
215// two non-data bytes (I use 0x31,0x60 here). A USB sniffer on Windows
216// might show a number of packets to you as if it was a large transfer
217// because of the way that Windows understands it: it _is_ a large
218// transfer until terminated with an USB packet smaller than 64 byte.
219//
220// b) The Windows driver expects to get some data packets (with at least
221// the two leading bytes 0x31,0x60) immediately after "resetting" the
222// FT chip and then in regular intervals. Otherwise a blue screen may
223// appear... In the code below, I make sure that every 10ms there is
224// some packet.
225//
226// c) Vendor specific commands to configure the FT245 are mostly ignored
227// in my code. Only those for reading the EEPROM are processed. See
228// DR_GetStatus and DR_VendorCmd below for my implementation.
229//
230// All other TD_ and DR_ functions remain as provided with CY3681.
231//
232//-----------------------------------------------------------------------------
233
234void usb_jtag_activity(void) // Called repeatedly while the device is idle
235{
236 if(!Running) return;
237
238 ProgIO_Poll();
239
240 if(!(EP1INCS & bmEPBUSY))
241 {
242 if(Pending > 0)
243 {
244 BYTE o, n;
245
246 AUTOPTRH2 = MSB( EP1INBUF );
247 AUTOPTRL2 = LSB( EP1INBUF );
248
249 XAUTODAT2 = 0x31;
250 XAUTODAT2 = 0x60;
251
252 if(Pending > 0x3E) { n = 0x3E; Pending -= n; }
253 else { n = Pending; Pending = 0; };
254
255 o = n;
256
257#ifdef USE_MOD256_OUTBUFFER
258 APTR1H = MSB( OutBuffer );
259 APTR1L = FirstDataInOutBuffer;
260 while(n--)
261 {
262 XAUTODAT2 = XAUTODAT1;
263 APTR1H = MSB( OutBuffer ); // Stay within 256-Byte-Buffer
264 };
265 FirstDataInOutBuffer = APTR1L;
266#else
267 APTR1H = MSB( &(OutBuffer[FirstDataInOutBuffer]) );
268 APTR1L = LSB( &(OutBuffer[FirstDataInOutBuffer]) );
269 while(n--)
270 {
271 XAUTODAT2 = XAUTODAT1;
272
273 if(++FirstDataInOutBuffer >= OUTBUFFER_LEN)
274 {
275 FirstDataInOutBuffer = 0;
276 APTR1H = MSB( OutBuffer );
277 APTR1L = LSB( OutBuffer );
278 };
279 };
280#endif
281 SYNCDELAY;
282 EP1INBC = 2 + o;
283 TF2 = 1; // Make sure there will be a short transfer soon
284 }
285 else if(TF2)
286 {
287 EP1INBUF[0] = 0x31;
288 EP1INBUF[1] = 0x60;
289 SYNCDELAY;
290 EP1INBC = 2;
291 TF2 = 0;
292 };
293 };
294
295 if(!(EP2468STAT & bmEP2EMPTY) && (Pending < OUTBUFFER_LEN-0x3F))
296 {
297 WORD i, n = EP2BCL|EP2BCH<<8;
298
299 APTR1H = MSB( EP2FIFOBUF );
300 APTR1L = LSB( EP2FIFOBUF );
301
302 for(i=0;i<n;)
303 {
304 if(ClockBytes > 0)
305 {
306 WORD m;
307
308 m = n-i;
309 if(ClockBytes < m) m = ClockBytes;
310 ClockBytes -= m;
311 i += m;
312
313 /* Shift out 8 bits from d */
314
315 if(WriteOnly) /* Shift out 8 bits from d */
316 {
317 while(m--) ProgIO_ShiftOut(XAUTODAT1);
318 }
319 else /* Shift in 8 bits at the other end */
320 {
321 while(m--) OutputByte(ProgIO_ShiftInOut(XAUTODAT1));
322 }
323 }
324 else
325 {
326 BYTE d = XAUTODAT1;
327 WriteOnly = (d & bmBIT6) ? FALSE : TRUE;
328
329 if(d & bmBIT7)
330 {
331 /* Prepare byte transfer, do nothing else yet */
332
333 ClockBytes = d & 0x3F;
334 }
335 else
336 {
337 if(WriteOnly)
338 ProgIO_Set_State(d);
339 else
340 OutputByte(ProgIO_Set_Get_State(d));
341 };
342 i++;
343 };
344 };
345
346 SYNCDELAY;
347 EP2BCL = 0x80; // Re-arm endpoint 2
348 };
349}
350
351//-----------------------------------------------------------------------------
352// Handler for Vendor Requests (
353//-----------------------------------------------------------------------------
354
355unsigned char app_vendor_cmd(void)
356{
357 // because of fx2/usb_common.c, this code returns nonzero on success
358 // OUT requests. Pretend we handle them all...
359
360 if ((bRequestType & bmRT_DIR_MASK) == bmRT_DIR_OUT)
361 {
362 if(bRequest == RQ_GET_STATUS)
363 {
364 Running = 1;
365 }
366
367 if (bRequest == VEN_SPI_WR) // 0x99
368 {
369 // get EP0 data
370 EP0BCL = 0; // arm EP0 for OUT xfer. This sets the busy bit
371
372 while (EP0CS & bmEPBUSY) // wait for busy to clear
373 ;
374
375 // head_hi, head_l , format , address, *buf , len
376 return !spi_write (wValueH, wValueL, wIndexH, wIndexL, EP0BUF, EP0BCL);
377 }
378
379
380 return 1;
381 }
382
383 // IN requests.
384
385 // change USB speed
386 if (bRequest == 0x91)
387 {
388 if (wIndexL == 0) // high speed
389 {
390 CT1 &= ~0x02;
391 fx2_renumerate(); // renumerate
392 }
393 else // full speed
394 {
395 CT1 |= 0x02;
396 fx2_renumerate(); // renumerate
397 }
398 }
399
400 // change JTAG enable
401 if (bRequest == 0x92)
402 {
403 if (wIndexL == 0) // FX2 is master of JTAG
404 {
405 IOC |= (1 << 7);
406 }
407 else // external connector is master of JTAG
408 {
409 IOC &= ~(1 << 7);
410 }
411 }
412 // change synchronous/asynchronous mode
413 if (bRequest == 0x93)
414 {
415 if(IFCONFIG & bmASYNC)
416 {
417 IFCONFIG &= ~bmASYNC;
418 }
419 else
420 {
421 IFCONFIG |= bmASYNC;
422 }
423 }
424
425 if (bRequest == 0x94) // change to synchronous mode
426 {
427 IFCONFIG &= ~bmASYNC;
428 }
429
430 if (bRequest == VEN_SPI_EN) // 0x96
431 {
432 SPI_OE |= bmSPI_OE; // PA.0,1,3,7 output enable
433 init_spi();
434 EP0BUF[0] = 0;
435 EP0BUF[1] = 0;
436 }
437
438 if (bRequest == VEN_SPI_DIS) // 0x97
439 {
440 SPI_OE &= ~bmSPI_OE; // PA.0,1,3,7 output disable
441 EP0BUF[0] = 0x42;
442 EP0BUF[1] = 0x43;
443 EP0BUF[2] = 0x42;
444 EP0BUF[3] = 0x43;
445 EP0BCH = 0;
446 EP0BCL = wLengthL;
447// EP0CS |= bmHSNAK; // Bram
448 return 1;
449 }
450
451 if (bRequest == VEN_SPI_RD) // 0x98
452 {
453 // header_H,header_L, format, address, *buf , len
454 if (spi_read (wValueH, wValueL, wIndexH, wIndexL, EP0BUF, wLengthL))
455 return 0;
456
457 EP0BCH = 0;
458 EP0BCL = wLengthL;
459 return 1;
460 }
461
462 if (bRequest == 0x95) // For debugging purposes
463 {
464
465 SPI &= ~bmSS; // enable slave select
466
467 spi_write_byte_msb(wValueL); // address
468 spi_write_byte_msb(wIndexL); // header
469 EP0BUF[0] = spi_read_byte_msb(); // read back value from slave
470
471 SPI |= bmSS; /* active low, disable slave */
472
473 EP0BCH = 0;
474 EP0BCL = 1; // Arm the EP
475 return 1;
476
477 /*static xdata unsigned char buf[2];
478 buf[0] = 0xFF;
479 buf[1] = 0x10;
480 spi_read(0x00, wValueL, SPI_FMT_HDR_1, wValueH, buf, 0);
481 //spi_write_byte_msb(wValueL);
482 EP0BUF[0] = 0x51;
483 EP0BUF[1] = wValueL;
484 EP0BCH = 0;
485 EP0BCL = wLengthL;
486 return 1;*/
487 }
488
489 if(bRequest == 0x90)
490 {
491 BYTE addr = (wIndexL<<1) & 0x7F;
492 EP0BUF[0] = eeprom[addr];
493 EP0BUF[1] = eeprom[addr+1];
494 }
495 else
496 {
497 // dummy data
498 EP0BUF[0] = 0x36;
499 EP0BUF[1] = 0x83;
500 }
501
502 EP0BCH = 0;
503 EP0BCL = (wLengthL<2) ? wLengthL : 2; // Arm endpoint with # bytes to transfer
504 //EP0CS |= bmHSNAK; // Bram
505
506 return 1;
507}
508
509//-----------------------------------------------------------------------------
510
511static void main_loop(void)
512{
513 while(1)
514 {
515 if(usb_setup_packet_avail()) usb_handle_setup_packet();
516 usb_jtag_activity();
517 }
518}
519
520//-----------------------------------------------------------------------------
521
522void main(void)
523{
524 EA = 0; // disable all interrupts
525
526 usb_jtag_init();
527 eeprom_init();
528 setup_autovectors ();
529 usb_install_handlers ();
530
531
532 EA = 1; // enable interrupts
533
534 fx2_renumerate(); // simulates disconnect / reconnect
535
536 main_loop();
537}
538
539
540
541
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