source: trunk/FirmwareFX2/usbjtag.c@ 135

Last change on this file since 135 was 135, checked in by demin, 13 years ago

remove unused vendor commands and set auto commit length to 512
File size: 14.3 KB
RevLine 
[4]1/*-----------------------------------------------------------------------------
2 * Code that turns a Cypress FX2 USB Controller into an USB JTAG adapter
3 *-----------------------------------------------------------------------------
4 * Copyright (C) 2005..2007 Kolja Waschk, ixo.de
5 *-----------------------------------------------------------------------------
6 * Check hardware.h/.c if it matches your hardware configuration (e.g. pinout).
7 * Changes regarding USB identification should be made in product.inc!
8 *-----------------------------------------------------------------------------
9 * This code is part of usbjtag. usbjtag is free software; you can redistribute
10 * it and/or modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the License,
12 * or (at your option) any later version. usbjtag is distributed in the hope
13 * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. You should have received a
16 * copy of the GNU General Public License along with this program in the file
17 * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
18 * St, Fifth Floor, Boston, MA 02110-1301 USA
19 *-----------------------------------------------------------------------------
20 */
21
22#include "isr.h"
23#include "timer.h"
24#include "delay.h"
25#include "fx2regs.h"
26#include "fx2utils.h"
27#include "usb_common.h"
28#include "usb_descriptors.h"
29#include "usb_requests.h"
30
31#include "syncdelay.h"
32
33#include "eeprom.h"
34#include "hardware.h"
35
36//-----------------------------------------------------------------------------
37// Define USE_MOD256_OUTBUFFER:
38// Saves about 256 bytes in code size, improves speed a little.
39// A further optimization could be not to use an extra output buffer at
40// all, but to write directly into EP1INBUF. Not implemented yet. When
41// downloading large amounts of data _to_ the target, there is no output
42// and thus the output buffer isn't used at all and doesn't slow down things.
43
44#define USE_MOD256_OUTBUFFER 1
45
46//-----------------------------------------------------------------------------
47// Global data
48
49typedef bit BOOL;
50#define FALSE 0
51#define TRUE 1
52static BOOL Running;
53static BOOL WriteOnly;
54
55static BYTE ClockBytes;
56static WORD Pending;
57
58#ifdef USE_MOD256_OUTBUFFER
59 static BYTE FirstDataInOutBuffer;
60 static BYTE FirstFreeInOutBuffer;
61#else
62 static WORD FirstDataInOutBuffer;
63 static WORD FirstFreeInOutBuffer;
64#endif
65
66#ifdef USE_MOD256_OUTBUFFER
67 /* Size of output buffer must be exactly 256 */
68 #define OUTBUFFER_LEN 0x100
69 /* Output buffer must begin at some address with lower 8 bits all zero */
70 xdata at 0xE000 BYTE OutBuffer[OUTBUFFER_LEN];
71#else
72 #define OUTBUFFER_LEN 0x200
73 static xdata BYTE OutBuffer[OUTBUFFER_LEN];
74#endif
75
76//-----------------------------------------------------------------------------
77
78void usb_jtag_init(void) // Called once at startup
79{
80 WORD tmp;
81
82 Running = FALSE;
83 ClockBytes = 0;
84 Pending = 0;
85 WriteOnly = TRUE;
86 FirstDataInOutBuffer = 0;
87 FirstFreeInOutBuffer = 0;
88
89 ProgIO_Init();
90
91 ProgIO_Enable();
92
93 // Make Timer2 reload at 100 Hz to trigger Keepalive packets
[21]94
[4]95 tmp = 65536 - ( 48000000 / 12 / 100 );
96 RCAP2H = tmp >> 8;
97 RCAP2L = tmp & 0xFF;
98 CKCON = 0; // Default Clock
99 T2CON = 0x04; // Auto-reload mode using internal clock, no baud clock.
100
101 // Enable Autopointer
102
[21]103 EXTACC = 1; // Enable
104 APTR1FZ = 1; // Don't freeze
105 APTR2FZ = 1; // Don't freeze
106
[4]107 // define endpoint configuration
108
109 REVCTL = 3; SYNCDELAY; // Allow FW access to FIFO buffer
110 FIFORESET = 0x80; SYNCDELAY; // From now on, NAK all, reset all FIFOS
111 FIFORESET = 0x02; SYNCDELAY; // Reset FIFO 2
112 FIFORESET = 0x04; SYNCDELAY; // Reset FIFO 4
113 FIFORESET = 0x06; SYNCDELAY; // Reset FIFO 6
114 FIFORESET = 0x08; SYNCDELAY; // Reset FIFO 8
115 FIFORESET = 0x00; SYNCDELAY; // Restore normal behaviour
116
117 EP1OUTCFG = 0xA0; SYNCDELAY; // Endpoint 1 Type Bulk
118 EP1INCFG = 0xA0; SYNCDELAY; // Endpoint 1 Type Bulk
[40]119
[4]120 EP2FIFOCFG = 0x00; SYNCDELAY; // Endpoint 2
121 EP2CFG = 0xA2; SYNCDELAY; // Endpoint 2 Valid, Out, Type Bulk, Double buffered
122
123 EP4FIFOCFG = 0x00; SYNCDELAY; // Endpoint 4 not used
124 EP4CFG = 0xA0; SYNCDELAY; // Endpoint 4 not used
[40]125
[4]126 REVCTL = 0; SYNCDELAY; // Reset FW access to FIFO buffer, enable auto-arming when AUTOOUT is switched to 1
127
128 EP6CFG = 0xA2; SYNCDELAY; // Out endpoint, Bulk, Double buffering
129 EP6FIFOCFG = 0x00; SYNCDELAY; // Firmware has to see a rising edge on auto bit to enable auto arming
[21]130 EP6FIFOCFG = bmAUTOOUT; SYNCDELAY; // Endpoint 6 used for user communicationn, auto commitment, 8 bits data bus
[4]131
132 EP8CFG = 0xE0; SYNCDELAY; // In endpoint, Bulk
133 EP8FIFOCFG = 0x00; SYNCDELAY; // Firmware has to see a rising edge on auto bit to enable auto arming
[21]134 EP8FIFOCFG = bmAUTOIN; SYNCDELAY; // Endpoint 8 used for user communication, auto commitment, 8 bits data bus
[4]135
[135]136 EP8AUTOINLENH = 0x02; SYNCDELAY; // Size in bytes of the IN data automatically commited (512 bytes here, but changed dynamically depending on the connection)
137 EP8AUTOINLENL = 0x00; SYNCDELAY; // Can use signal PKTEND if you want to commit a shorter packet
[4]138
139 // Out endpoints do not come up armed
140 // Since the defaults are double buffered we must write dummy byte counts twice
[135]141 EP2BCL = 0x80; SYNCDELAY; // Arm EP2OUT by writing byte count w/skip.
[4]142 EP4BCL = 0x80; SYNCDELAY;
[135]143 EP2BCL = 0x80; SYNCDELAY; // Arm EP4OUT by writing byte count w/skip.
[4]144 EP4BCL = 0x80; SYNCDELAY;
[21]145
[40]146 PINFLAGSAB = 0xFA; SYNCDELAY; // 1111_1010 => FLAGA = EMPTY flag for EP6; FLAGB = FULL flag for EP8
[26]147
[40]148 // LED turned off by default
149 IOD |= (1 << 4); SYNCDELAY;
150
[4]151 // Put the system in high speed by default (REM: USB-Blaster is in full speed)
152 // This can be changed by vendor commands
153 CT1 &= ~0x02;
154}
155
156void OutputByte(BYTE d)
157{
158#ifdef USE_MOD256_OUTBUFFER
159 OutBuffer[FirstFreeInOutBuffer] = d;
160 FirstFreeInOutBuffer = ( FirstFreeInOutBuffer + 1 ) & 0xFF;
161#else
162 OutBuffer[FirstFreeInOutBuffer++] = d;
163 if(FirstFreeInOutBuffer >= OUTBUFFER_LEN) FirstFreeInOutBuffer = 0;
164#endif
165 Pending++;
166}
167
168//-----------------------------------------------------------------------------
169// usb_jtag_activity does most of the work. It now happens to behave just like
170// the combination of FT245BM and Altera-programmed EPM7064 CPLD in Altera's
171// USB-Blaster. The CPLD knows two major modes: Bit banging mode and Byte
172// shift mode. It starts in Bit banging mode. While bytes are received
173// from the host on EP2OUT, each byte B of them is processed as follows:
174//
175// Please note: nCE, nCS, LED pins and DATAOUT actually aren't supported here.
176// Support for these would be required for AS/PS mode and isn't too complicated,
177// but I haven't had the time yet.
178//
179// Bit banging mode:
180//
181// 1. Remember bit 6 (0x40) in B as the "Read bit".
182//
183// 2. If bit 7 (0x40) is set, switch to Byte shift mode for the coming
184// X bytes ( X := B & 0x3F ), and don't do anything else now.
185//
186// 3. Otherwise, set the JTAG signals as follows:
187// TCK/DCLK high if bit 0 was set (0x01), otherwise low
188// TMS/nCONFIG high if bit 1 was set (0x02), otherwise low
189// nCE high if bit 2 was set (0x04), otherwise low
190// nCS high if bit 3 was set (0x08), otherwise low
191// TDI/ASDI/DATA0 high if bit 4 was set (0x10), otherwise low
192// Output Enable/LED active if bit 5 was set (0x20), otherwise low
193//
194// 4. If "Read bit" (0x40) was set, record the state of TDO(CONF_DONE) and
195// DATAOUT(nSTATUS) pins and put it as a byte ((DATAOUT<<1)|TDO) in the
196// output FIFO _to_ the host (the code here reads TDO only and assumes
197// DATAOUT=1)
198//
199// Byte shift mode:
200//
201// 1. Load shift register with byte from host
202//
203// 2. Do 8 times (i.e. for each bit of the byte; implemented in shift.a51)
204// 2a) if nCS=1, set carry bit from TDO, else set carry bit from DATAOUT
205// 2b) Rotate shift register through carry bit
206// 2c) TDI := Carry bit
207// 2d) Raise TCK, then lower TCK.
208//
209// 3. If "Read bit" was set when switching into byte shift mode,
210// record the shift register content and put it into the FIFO
211// _to_ the host.
212//
213// Some more (minor) things to consider to emulate the FT245BM:
214//
215// a) The FT245BM seems to transmit just packets of no more than 64 bytes
216// (which perfectly matches the USB spec). Each packet starts with
217// two non-data bytes (I use 0x31,0x60 here). A USB sniffer on Windows
218// might show a number of packets to you as if it was a large transfer
219// because of the way that Windows understands it: it _is_ a large
220// transfer until terminated with an USB packet smaller than 64 byte.
221//
222// b) The Windows driver expects to get some data packets (with at least
223// the two leading bytes 0x31,0x60) immediately after "resetting" the
224// FT chip and then in regular intervals. Otherwise a blue screen may
225// appear... In the code below, I make sure that every 10ms there is
226// some packet.
227//
228// c) Vendor specific commands to configure the FT245 are mostly ignored
229// in my code. Only those for reading the EEPROM are processed. See
230// DR_GetStatus and DR_VendorCmd below for my implementation.
231//
232// All other TD_ and DR_ functions remain as provided with CY3681.
233//
234//-----------------------------------------------------------------------------
235
236void usb_jtag_activity(void) // Called repeatedly while the device is idle
237{
238 if(!Running) return;
239
240 ProgIO_Poll();
241
242 if(!(EP1INCS & bmEPBUSY))
243 {
244 if(Pending > 0)
245 {
246 BYTE o, n;
247
248 AUTOPTRH2 = MSB( EP1INBUF );
249 AUTOPTRL2 = LSB( EP1INBUF );
250
251 XAUTODAT2 = 0x31;
252 XAUTODAT2 = 0x60;
253
254 if(Pending > 0x3E) { n = 0x3E; Pending -= n; }
255 else { n = Pending; Pending = 0; };
256
257 o = n;
258
259#ifdef USE_MOD256_OUTBUFFER
260 APTR1H = MSB( OutBuffer );
261 APTR1L = FirstDataInOutBuffer;
262 while(n--)
263 {
264 XAUTODAT2 = XAUTODAT1;
265 APTR1H = MSB( OutBuffer ); // Stay within 256-Byte-Buffer
266 };
267 FirstDataInOutBuffer = APTR1L;
268#else
269 APTR1H = MSB( &(OutBuffer[FirstDataInOutBuffer]) );
270 APTR1L = LSB( &(OutBuffer[FirstDataInOutBuffer]) );
271 while(n--)
272 {
273 XAUTODAT2 = XAUTODAT1;
274
275 if(++FirstDataInOutBuffer >= OUTBUFFER_LEN)
276 {
277 FirstDataInOutBuffer = 0;
278 APTR1H = MSB( OutBuffer );
279 APTR1L = LSB( OutBuffer );
280 };
281 };
282#endif
283 SYNCDELAY;
284 EP1INBC = 2 + o;
285 TF2 = 1; // Make sure there will be a short transfer soon
286 }
287 else if(TF2)
288 {
289 EP1INBUF[0] = 0x31;
290 EP1INBUF[1] = 0x60;
291 SYNCDELAY;
292 EP1INBC = 2;
293 TF2 = 0;
294 };
295 };
296
297 if(!(EP2468STAT & bmEP2EMPTY) && (Pending < OUTBUFFER_LEN-0x3F))
298 {
299 WORD i, n = EP2BCL|EP2BCH<<8;
300
301 APTR1H = MSB( EP2FIFOBUF );
302 APTR1L = LSB( EP2FIFOBUF );
303
304 for(i=0;i<n;)
305 {
306 if(ClockBytes > 0)
307 {
308 WORD m;
309
310 m = n-i;
311 if(ClockBytes < m) m = ClockBytes;
312 ClockBytes -= m;
313 i += m;
314
315 /* Shift out 8 bits from d */
316
317 if(WriteOnly) /* Shift out 8 bits from d */
318 {
319 while(m--) ProgIO_ShiftOut(XAUTODAT1);
320 }
321 else /* Shift in 8 bits at the other end */
322 {
323 while(m--) OutputByte(ProgIO_ShiftInOut(XAUTODAT1));
324 }
325 }
326 else
327 {
328 BYTE d = XAUTODAT1;
329 WriteOnly = (d & bmBIT6) ? FALSE : TRUE;
330
331 if(d & bmBIT7)
332 {
333 /* Prepare byte transfer, do nothing else yet */
334
335 ClockBytes = d & 0x3F;
336 }
337 else
338 {
339 if(WriteOnly)
340 ProgIO_Set_State(d);
341 else
342 OutputByte(ProgIO_Set_Get_State(d));
343 };
344 i++;
345 };
346 };
347
348 SYNCDELAY;
349 EP2BCL = 0x80; // Re-arm endpoint 2
350 };
351}
352
353//-----------------------------------------------------------------------------
354// Handler for Vendor Requests (
355//-----------------------------------------------------------------------------
356
357unsigned char app_vendor_cmd(void)
358{
359 // because of fx2/usb_common.c, this code returns nonzero on success
360 // OUT requests. Pretend we handle them all...
361
362 if ((bRequestType & bmRT_DIR_MASK) == bmRT_DIR_OUT)
363 {
364 if(bRequest == RQ_GET_STATUS)
365 {
366 Running = 1;
367 }
368
369 return 1;
370 }
371
372 // IN requests.
373
374 if(bRequest == 0x90)
375 {
376 BYTE addr = (wIndexL<<1) & 0x7F;
377 EP0BUF[0] = eeprom[addr];
378 EP0BUF[1] = eeprom[addr+1];
379 }
380 else
381 {
382 // dummy data
383 EP0BUF[0] = 0x36;
384 EP0BUF[1] = 0x83;
385 }
386
387 EP0BCH = 0;
388 EP0BCL = (wLengthL<2) ? wLengthL : 2; // Arm endpoint with # bytes to transfer
389
390 return 1;
391}
392
393//-----------------------------------------------------------------------------
394
395static void main_loop(void)
396{
397 while(1)
398 {
399 if(usb_setup_packet_avail()) usb_handle_setup_packet();
400 usb_jtag_activity();
401 }
402}
403
404//-----------------------------------------------------------------------------
405
406void main(void)
407{
408 EA = 0; // disable all interrupts
409
410 usb_jtag_init();
411 eeprom_init();
[21]412 setup_autovectors();
413 usb_install_handlers();
[4]414
415
416 EA = 1; // enable interrupts
417
418 fx2_renumerate(); // simulates disconnect / reconnect
419
420 main_loop();
421}
422
423
424
425
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