| [4] | 1 | usb_jtag using Cypress FX2 chip
|
|---|
| 2 | ===============================
|
|---|
| 3 |
|
|---|
| [5] | 4 | == General information ==
|
|---|
| [4] | 5 |
|
|---|
| [5] | 6 | The code in this directory is for Cypress FX2 (e.g. CY7C68013A) and can be
|
|---|
| 7 | compiled with the SDCC compiler (I tried version 2.6 as shipped with Ubuntu
|
|---|
| 8 | 6.10). Once I had a version that could be compiled with Keil tools (until early
|
|---|
| 9 | 2007), but switched to SDCC because I usually develop on a Linux host.
|
|---|
| [4] | 10 |
|
|---|
| [5] | 11 | No logic beside the FX2 itself and only a few external components are required
|
|---|
| 12 | for a basic JTAG adapter. I don't have detailed schematics available; my test
|
|---|
| 13 | setup consists of a FX2 on a custom board where it's directly connected to a
|
|---|
| 14 | Cyclone FPGA.
|
|---|
| 15 |
|
|---|
| [4] | 16 | ____________
|
|---|
| 17 | | |
|
|---|
| 18 | | Cypress |
|
|---|
| 19 | USB__| EZ-USB FX2 |__JTAG(TDI,TDO,TCK,TMS)
|
|---|
| 20 | | CY7C68013A |
|
|---|
| 21 | |____________|
|
|---|
| 22 | __|__________
|
|---|
| 23 | | |
|
|---|
| 24 | | 24 MHz XTAL |
|
|---|
| 25 | |_____________|
|
|---|
| 26 |
|
|---|
| 27 |
|
|---|
| [5] | 28 | Similar boards are available from fpga4fun.com - the boards named "Saxo-L" and
|
|---|
| 29 | "Xylo-EM" are pre-wired for use with an adapted version of my code, while
|
|---|
| 30 | "Saxo" and "Xylo" can be used after soldering 4 extra wires:
|
|---|
| [4] | 31 |
|
|---|
| 32 | http://www.fpga4fun.com/board_Xylo.html
|
|---|
| 33 |
|
|---|
| [5] | 34 | There's a discussion thread in the fpga4fun forum about this firmware:
|
|---|
| [4] | 35 |
|
|---|
| [5] | 36 | http://www.fpga4fun.com/forum/viewtopic.php?t=483
|
|---|
| 37 |
|
|---|
| 38 |
|
|---|
| 39 | == Adapting the code to your hardware ==
|
|---|
| 40 |
|
|---|
| [4] | 41 | As is, the code assumes the following pin assignment:
|
|---|
| 42 |
|
|---|
| 43 | Port C.0: TDI
|
|---|
| 44 | Port C.1: TDO
|
|---|
| 45 | Port C.2: TCK
|
|---|
| 46 | Port C.3: TMS
|
|---|
| 47 |
|
|---|
| [5] | 48 | Other assignments are possible. If you have your signals connected to
|
|---|
| 49 | bit-addressable I/O pins (port A,B,C or D), I suggest you make a copy of
|
|---|
| 50 | hw_basic.c and adapt the definitions and ProgIO_Init() in it to your needs.
|
|---|
| 51 | The file hw_saxo_l is even simpler to adapt if you want only JTAG and no AS/PS
|
|---|
| 52 | mode. If your signals are not on bit-addressable I/Os (that is, you're using
|
|---|
| 53 | port E), you could base your adaptation on the slower hw_xpcu_i.c. You may
|
|---|
| 54 | specify the name of your adapted hardware-specific file when "make"ing, e.g.:
|
|---|
| [4] | 55 |
|
|---|
| [5] | 56 | make HARDWARE=hw_saxo_l
|
|---|
| [4] | 57 |
|
|---|
| 58 |
|
|---|
| [5] | 59 | The USB identification data (vendor/product ID, strings, ...) can be modified
|
|---|
| 60 | in dscr.a51. The firmware emulates the 128 byte EEPROM that usually holds
|
|---|
| 61 | configuration data for the FT245 and which can be read from the host; its
|
|---|
| 62 | content (including checksum) is computed from the data in dscr.a51 as well.
|
|---|
| [4] | 63 |
|
|---|
| [5] | 64 | The WAKEUP pin should be high for the re-numeration to work reliably (thanks
|
|---|
| 65 | Jean/fpga4fun!).
|
|---|
| 66 |
|
|---|
| 67 |
|
|---|
| 68 | == Using it with Xilinx JTAG cable ==
|
|---|
| 69 |
|
|---|
| 70 | There is code to support running in the "Xilinx Platform Cable USB". If you
|
|---|
| 71 | select HARDWARE=hw_xpcu_i or hw_xpcu_x at the top of the Makefile, a firmware
|
|---|
| 72 | for the XPCU will be built. I've tested this only with unmodified CPLD version
|
|---|
| 73 | 18 (0x12) on a Spartan-3E starter kit, as it was programmed by my WebPack 8.2i.
|
|---|
| 74 | The code needs optimization; yet it is merely a proof of concept.
|
|---|
| 75 | Compile for the XPCU with e.g. "make HARDWARE=hw_xpcu_x".
|
|---|
| 76 |
|
|---|
| [4] | 77 | hw_xpcu_i: Access "internal" chain (the XPCU CPLD, IC3, itself)
|
|---|
| 78 | hw_xpcu_x: Access "external" chain (the Spartan 3E, PROM, etc.)
|
|---|
| 79 |
|
|---|
| [5] | 80 |
|
|---|
| 81 | == History ==
|
|---|
| 82 |
|
|---|
| 83 | Changes since previous release on 2007-02-15:
|
|---|
| 84 | - Jean Nicolle contributed hw_saxo_l.c for the FX2 boards from fpga4fun.com
|
|---|
| 85 | - fx2/Makefile fixed to build correct libfx2.lib even under Windows.
|
|---|
| 86 |
|
|---|
| [4] | 87 | Changes since previous release on 2007-01-28:
|
|---|
| 88 | - Initial suppport for running on Xilinx XPCU.
|
|---|
| 89 | - New FX2 code, based on USRP2 from the GNU Radio Project;
|
|---|
| 90 | - Firmware can now be compiled using SDCC 2.6. No more Keil support.
|
|---|
| [5] | 91 | - EEPROM content is automatically computed from dscr.a51, including checksum.
|
|---|
| [4] | 92 |
|
|---|
| 93 | Changes since initial release on 2006-04-23:
|
|---|
| 94 | - added this readme.txt
|
|---|
| [5] | 95 | - reorganized my project folder: diff now created from Subversion repository
|
|---|
| [4] | 96 | - stripped *.dist extension from eeprom.c and dscr.a51
|
|---|
| 97 | - added unique proper product and vendor ID (thanks to Antti Lukats!)
|
|---|
| 98 | - fixed checksum in eeprom.c
|
|---|
| 99 | - added comments about AS/PS mode pins in usbjtag.c
|
|---|
| 100 |
|
|---|
| 101 |
|
|---|
| 102 |
|
|---|
| 103 |
|
|---|
