source: trunk/FirmwareFX2/hw_basic.c@ 162

Last change on this file since 162 was 32, checked in by demin, 15 years ago

change LED polarity

File size: 6.2 KB
RevLine 
[9]1/*-----------------------------------------------------------------------------
2 * Hardware-dependent code for usb_jtag
3 *-----------------------------------------------------------------------------
4 * Copyright (C) 2007 Kolja Waschk, ixo.de
5 *-----------------------------------------------------------------------------
6 * This code is part of usbjtag. usbjtag is free software; you can redistribute
7 * it and/or modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the License,
9 * or (at your option) any later version. usbjtag is distributed in the hope
10 * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
11 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. You should have received a
13 * copy of the GNU General Public License along with this program in the file
14 * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
15 * St, Fifth Floor, Boston, MA 02110-1301 USA
16 *-----------------------------------------------------------------------------
17 */
18
19#include <fx2regs.h>
20#include "hardware.h"
21#include "delay.h"
22
23//-----------------------------------------------------------------------------
24
25#define HAVE_OE_LED 1
26
27//-----------------------------------------------------------------------------
28
[19]29/* JTAG TDI */
[9]30
31sbit at 0xB3 TDI; /* Port D.3 */
[19]32#define bmTDIOE bmBIT3
[9]33#define SetTDI(x) do{TDI=(x);}while(0)
34
[19]35/* JTAG TCK */
[9]36
37sbit at 0xB2 TCK; /* Port D.2 */
[19]38#define bmTCKOE bmBIT2
[9]39#define SetTCK(x) do{TCK=(x);}while(0)
40
[19]41/* JTAG TMS */
[9]42
43sbit at 0xB1 TMS; /* Port D.1 */
[19]44#define bmTMSOE bmBIT1
[9]45#define SetTMS(x) do{TMS=(x);}while(0)
46
[19]47/* JTAG TDO */
[9]48
49sbit at 0xB0 TDO; /* Port D.0 */
[19]50#define bmTDOOE bmBIT0
[9]51#define GetTDO(x) TDO
52
53//-----------------------------------------------------------------------------
54
55#ifdef HAVE_OE_LED
56
57 sbit at 0xB4 OELED; /* Port D.4 */
[19]58 #define bmOELEDOE bmBIT4
[9]59 #define SetOELED(x) do{OELED=(x);}while(0)
60
61#else
62
63 #define bmOELEDOE 0
64 #define SetOELED(x) while(0){}
65
66#endif
67
68//-----------------------------------------------------------------------------
69
70#define bmPROGOUTOE (bmTCKOE|bmTDIOE|bmTMSOE|bmOELEDOE)
71#define bmPROGINOE (bmTDOOE)
72
73//-----------------------------------------------------------------------------
74
75void ProgIO_Poll(void) {}
76// These aren't called anywhere in usbjtag.c, but I plan to do so...
77void ProgIO_Enable(void) {}
78void ProgIO_Disable(void) {}
79void ProgIO_Deinit(void) {}
80
81
82void ProgIO_Init(void)
83{
84 /* The following code depends on your actual circuit design.
85 Make required changes _before_ you try the code! */
86
87 // set the CPU clock to 48MHz, enable clock output to FPGA
88 CPUCS = bmCLKOE | bmCLKSPD1;
89
[23]90 // put the system in FIFO mode by default
91 // internal clock source at 48Mhz, drive output pin, synchronous mode
92 // NOTE: Altera USB-Blaster does not work in another mode
[19]93 IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmIFCFG1 | bmIFCFG0;
[9]94
[19]95 // Output enable (TDO input, others output)
[9]96 OED = (OED&~bmPROGINOE) | bmPROGOUTOE;
97}
98
99void ProgIO_Set_State(unsigned char d)
100{
101 /* Set state of output pins:
102 *
103 * d.0 => TCK
104 * d.1 => TMS
105 * d.4 => TDI
106 * d.5 => LED / Output Enable
107 */
108
109 SetTCK((d & bmBIT0) ? 1 : 0);
110 SetTMS((d & bmBIT1) ? 1 : 0);
111 SetTDI((d & bmBIT4) ? 1 : 0);
112#ifdef HAVE_OE_LED
[32]113 SetOELED((d & bmBIT5) ? 0 : 1);
[9]114#endif
115}
116
117unsigned char ProgIO_Set_Get_State(unsigned char d)
118{
119 /* Set state of output pins (s.a.)
120 * then read state of input pins:
121 *
122 * TDO => d.0
123 */
124
125 ProgIO_Set_State(d);
[19]126 return 2|GetTDO();
[9]127}
128
129//-----------------------------------------------------------------------------
130
131void ProgIO_ShiftOut(unsigned char c)
132{
[19]133 /* Shift out byte C:
[9]134 *
135 * 8x {
136 * Output least significant bit on TDI
137 * Raise TCK
138 * Shift c right
139 * Lower TCK
140 * }
141 */
142
143 (void)c; /* argument passed in DPL */
144
145 _asm
146 MOV A,DPL
147 ;; Bit0
148 RRC A
149 MOV _TDI,C
150 SETB _TCK
151 ;; Bit1
152 RRC A
153 CLR _TCK
154 MOV _TDI,C
155 SETB _TCK
156 ;; Bit2
157 RRC A
158 CLR _TCK
159 MOV _TDI,C
160 SETB _TCK
161 ;; Bit3
162 RRC A
163 CLR _TCK
164 MOV _TDI,C
165 SETB _TCK
166 ;; Bit4
167 RRC A
168 CLR _TCK
169 MOV _TDI,C
170 SETB _TCK
171 ;; Bit5
172 RRC A
173 CLR _TCK
174 MOV _TDI,C
175 SETB _TCK
176 ;; Bit6
177 RRC A
178 CLR _TCK
179 MOV _TDI,C
180 SETB _TCK
181 ;; Bit7
182 RRC A
183 CLR _TCK
184 MOV _TDI,C
185 SETB _TCK
186 NOP
187 CLR _TCK
188 ret
189 _endasm;
190}
191
192/*
193;; For ShiftInOut, the timing is a little more
194;; critical because we have to read _TDO/shift/set _TDI
195;; when _TCK is low. But 20% duty cycle at 48/4/5 MHz
196;; is just like 50% at 6 Mhz, and that's still acceptable
197*/
198
199unsigned char ProgIO_ShiftInOut(unsigned char c)
200{
201 /* Shift out byte C, shift in from TDO:
202 *
203 * 8x {
204 * Read carry from TDO
205 * Output least significant bit on TDI
206 * Raise TCK
207 * Shift c right, append carry (TDO) at left
208 * Lower TCK
209 * }
210 * Return c.
211 */
212
213 (void)c; /* argument passed in DPL */
214
215 _asm
216 MOV A,DPL
217
218 ;; Bit0
219 MOV C,_TDO
220 RRC A
221 MOV _TDI,C
222 SETB _TCK
223 CLR _TCK
224 ;; Bit1
225 MOV C,_TDO
226 RRC A
227 MOV _TDI,C
228 SETB _TCK
229 CLR _TCK
230 ;; Bit2
231 MOV C,_TDO
232 RRC A
233 MOV _TDI,C
234 SETB _TCK
235 CLR _TCK
236 ;; Bit3
237 MOV C,_TDO
238 RRC A
239 MOV _TDI,C
240 SETB _TCK
241 CLR _TCK
242 ;; Bit4
243 MOV C,_TDO
244 RRC A
245 MOV _TDI,C
246 SETB _TCK
247 CLR _TCK
248 ;; Bit5
249 MOV C,_TDO
250 RRC A
251 MOV _TDI,C
252 SETB _TCK
253 CLR _TCK
254 ;; Bit6
255 MOV C,_TDO
256 RRC A
257 MOV _TDI,C
258 SETB _TCK
259 CLR _TCK
260 ;; Bit7
261 MOV C,_TDO
262 RRC A
263 MOV _TDI,C
264 SETB _TCK
265 CLR _TCK
266
267 MOV DPL,A
268 ret
269 _endasm;
270
271 /* return value in DPL */
272
273 return c;
274}
275
276
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